/***************************************************************************
 *                      COPYRIGHT NOTICE
 *             Copyright 2019 Horizon Robotics, Inc.
 *                     All rights reserved.
 ***************************************************************************/

#ifndef __HOBOT_IPU_REG_H__
#define __HOBOT_IPU_REG_H__

#include "vio_hw_common_api.h"
#include "hobot_dev_ipu.h"

enum ipu_shadow_id{
	SDW_ID_0,
	SDW_ID_1,
	SDW_ID_2,
	SDW_ID_3,
	SDW_ID_END,
};

enum ipu_reg {
	IPU_0_SRC_WIDTH,
	IPU_0_SRC_HEIGHT,
	IPU_0_RD_DDR_STRIDE_LEN_Y,
	IPU_0_RD_DDR_STRIDE_LEN_UV,
	IPU_0_US_ROI_EN,
	IPU_0_US_ROI_SIZE,
	IPU_0_DS_0_ROI_EN,
	IPU_0_DS_0_ROI_SIZE,
	IPU_0_DS_1_ROI_EN,
	IPU_0_DS_1_ROI_SIZE,
	IPU_0_DS_2_ROI_EN,
	IPU_0_DS_2_ROI_SIZE,
	IPU_0_DS_3_ROI_EN,
	IPU_0_DS_3_ROI_SIZE,
	IPU_0_DS_4_ROI_EN,
	IPU_0_DS_4_ROI_SIZE,
	IPU_0_US_EN,
	IPU_0_US_STEP,
	IPU_0_DS_0_EN,
	IPU_0_DS_0_STEP,
	IPU_0_DS_1_EN,
	IPU_0_DS_1_STEP,
	IPU_0_DS_2_EN,
	IPU_0_DS_2_STEP,
	IPU_0_DS_3_EN,
	IPU_0_DS_3_STEP,
	IPU_0_DS_4_EN,
	IPU_0_DS_4_STEP,
	IPU_0_OSD_EN,
	IPU_0_OSD_0_ROI_0_START,
	IPU_0_OSD_0_ROI_0_SIZE,
	IPU_0_OSD_0_ROI_1_START,
	IPU_0_OSD_0_ROI_1_SIZE, 
	IPU_0_OSD_0_ROI_2_START,
	IPU_0_OSD_0_ROI_2_SIZE,
	IPU_0_OSD_1_ROI_0_START,
	IPU_0_OSD_1_ROI_0_SIZE,
	IPU_0_OSD_1_ROI_1_START,
	IPU_0_OSD_1_ROI_1_SIZE,
	IPU_0_OSD_1_ROI_2_START,
	IPU_0_OSD_1_ROI_2_SIZE,
	IPU_0_OSD_2_ROI_0_START,
	IPU_0_OSD_2_ROI_0_SIZE,
	IPU_0_OSD_2_ROI_1_START,
	IPU_0_OSD_2_ROI_1_SIZE,
	IPU_0_OSD_2_ROI_2_START,
	IPU_0_OSD_2_ROI_2_SIZE,
	IPU_0_OSD_STA_ENABLE,
	IPU_0_OSD_0_STA_ROI_0_START,
	IPU_0_OSD_0_STA_ROI_0_SIZE,
	IPU_0_OSD_0_STA_ROI_1_START,
	IPU_0_OSD_0_STA_ROI_1_SIZE,
	IPU_0_OSD_0_STA_ROI_2_START,
	IPU_0_OSD_0_STA_ROI_2_SIZE,
	IPU_0_OSD_0_STA_ROI_3_START,
	IPU_0_OSD_0_STA_ROI_3_SIZE,
	IPU_0_OSD_0_STA_ROI_4_START,
	IPU_0_OSD_0_STA_ROI_4_SIZE,
	IPU_0_OSD_0_STA_ROI_5_START,
	IPU_0_OSD_0_STA_ROI_5_SIZE,
	IPU_0_OSD_0_STA_ROI_6_START,
	IPU_0_OSD_0_STA_ROI_6_SIZE,
	IPU_0_OSD_0_STA_ROI_7_START,
	IPU_0_OSD_0_STA_ROI_7_SIZE,
	IPU_0_OSD_1_STA_ROI_0_START,
	IPU_0_OSD_1_STA_ROI_0_SIZE,
	IPU_0_OSD_1_STA_ROI_1_START,
	IPU_0_OSD_1_STA_ROI_1_SIZE,
	IPU_0_OSD_1_STA_ROI_2_START,
	IPU_0_OSD_1_STA_ROI_2_SIZE,
	IPU_0_OSD_1_STA_ROI_3_START,
	IPU_0_OSD_1_STA_ROI_3_SIZE,
	IPU_0_OSD_1_STA_ROI_4_START,
	IPU_0_OSD_1_STA_ROI_4_SIZE,
	IPU_0_OSD_1_STA_ROI_5_START,
	IPU_0_OSD_1_STA_ROI_5_SIZE,
	IPU_0_OSD_1_STA_ROI_6_START,
	IPU_0_OSD_1_STA_ROI_6_SIZE,
	IPU_0_OSD_1_STA_ROI_7_START,
	IPU_0_OSD_1_STA_ROI_7_SIZE,
	IPU_0_OSD_2_STA_ROI_0_START,
	IPU_0_OSD_2_STA_ROI_0_SIZE,
	IPU_0_OSD_2_STA_ROI_1_START,
	IPU_0_OSD_2_STA_ROI_1_SIZE,
	IPU_0_OSD_2_STA_ROI_2_START,
	IPU_0_OSD_2_STA_ROI_2_SIZE,
	IPU_0_OSD_2_STA_ROI_3_START,
	IPU_0_OSD_2_STA_ROI_3_SIZE,
	IPU_0_OSD_2_STA_ROI_4_START,
	IPU_0_OSD_2_STA_ROI_4_SIZE,
	IPU_0_OSD_2_STA_ROI_5_START,
	IPU_0_OSD_2_STA_ROI_5_SIZE,
	IPU_0_OSD_2_STA_ROI_6_START,
	IPU_0_OSD_2_STA_ROI_6_SIZE,
	IPU_0_OSD_2_STA_ROI_7_START,
	IPU_0_OSD_2_STA_ROI_7_SIZE,
	IPU_0_OSD_STA_LEVEL,
	IPU_0_OSD_0_ROI_0_ADDR,
	IPU_0_OSD_0_ROI_1_ADDR,
	IPU_0_OSD_0_ROI_2_ADDR,
	IPU_0_OSD_1_ROI_0_ADDR,
	IPU_0_OSD_1_ROI_1_ADDR,
	IPU_0_OSD_1_ROI_2_ADDR,
	IPU_0_OSD_2_ROI_0_ADDR,
	IPU_0_OSD_2_ROI_1_ADDR,
	IPU_0_OSD_2_ROI_2_ADDR,
	IPU_0_US_DDR_STRIDE_LEN_Y,
	IPU_0_US_DDR_STRIDE_LEN_UV,
	IPU_0_DS_0_DDR_STRIDE_LEN_Y,
	IPU_0_DS_0_DDR_STRIDE_LEN_UV,
	IPU_0_DS_1_DDR_STRIDE_LEN_Y,
	IPU_0_DS_1_DDR_STRIDE_LEN_UV,
	IPU_0_DS_2_DDR_STRIDE_LEN_Y,
	IPU_0_DS_2_DDR_STRIDE_LEN_UV,
	IPU_0_DS_3_DDR_STRIDE_LEN_Y,
	IPU_0_DS_3_DDR_STRIDE_LEN_UV,
	IPU_0_DS_4_DDR_STRIDE_LEN_Y,
	IPU_0_DS_4_DDR_STRIDE_LEN_UV,
	IPU_SIZE_ERR,
	IPU_CHECKSUM_Y,
	IPU_CHECKSUM_UV,
	IPU_SCALE_STATE,
	IPU_LAYER_0_WR_RD_LINE_CNT,
	IPU_LAYER_1_WR_RD_LINE_CNT,
	IPU_LAYER_2_WR_RD_LINE_CNT,
	IPU_LAYER_0_REQ_LINE_CNT,
	IPU_LAYER_1_REQ_LINE_CNT,
	IPU_LAYER_2_REQ_LINE_CNT,
	IPU_ERR_CLR,
	IPU_ERR_STATUS,
	IPU_WR_DDR_FIFO_THRED_0,
	IPU_WR_DDR_FIFO_THRED_1,
	/*0x404*/
	IPU_1_SRC_WIDTH,
	IPU_1_SRC_HEIGHT,
	IPU_1_RD_DDR_STRIDE_LEN_Y,
	IPU_1_RD_DDR_STRIDE_LEN_UV,
	IPU_1_US_ROI_EN,
	IPU_1_US_ROI_SIZE,
	IPU_1_DS_0_ROI_EN,
	IPU_1_DS_0_ROI_SIZE,
	IPU_1_DS_1_ROI_EN,
	IPU_1_DS_1_ROI_SIZE,
	IPU_1_DS_2_ROI_EN,
	IPU_1_DS_2_ROI_SIZE,
	IPU_1_DS_3_ROI_EN,
	IPU_1_DS_3_ROI_SIZE,
	IPU_1_DS_4_ROI_EN,
	IPU_1_DS_4_ROI_SIZE,
	IPU_1_US_EN,
	IPU_1_US_STEP,
	IPU_1_DS_0_EN,
	IPU_1_DS_0_STEP,
	IPU_1_DS_1_EN,
	IPU_1_DS_1_STEP,
	IPU_1_DS_2_EN,
	IPU_1_DS_2_STEP,
	IPU_1_DS_3_EN,
	IPU_1_DS_3_STEP,
	IPU_1_DS_4_EN,
	IPU_1_DS_4_STEP,
	IPU_1_OSD_EN,
	IPU_1_OSD_0_ROI_0_START,
	IPU_1_OSD_0_ROI_0_SIZE,
	IPU_1_OSD_0_ROI_1_START,
	IPU_1_OSD_0_ROI_1_SIZE, 
	IPU_1_OSD_0_ROI_2_START,
	IPU_1_OSD_0_ROI_2_SIZE,
	IPU_1_OSD_1_ROI_0_START,
	IPU_1_OSD_1_ROI_0_SIZE,
	IPU_1_OSD_1_ROI_1_START,
	IPU_1_OSD_1_ROI_1_SIZE,
	IPU_1_OSD_1_ROI_2_START,
	IPU_1_OSD_1_ROI_2_SIZE,
	IPU_1_OSD_2_ROI_0_START,
	IPU_1_OSD_2_ROI_0_SIZE,
	IPU_1_OSD_2_ROI_1_START,
	IPU_1_OSD_2_ROI_1_SIZE,
	IPU_1_OSD_2_ROI_2_START,
	IPU_1_OSD_2_ROI_2_SIZE,
	IPU_1_OSD_STA_ENABLE,
	IPU_1_OSD_0_STA_ROI_0_START,
	IPU_1_OSD_0_STA_ROI_0_SIZE,
	IPU_1_OSD_0_STA_ROI_1_START,
	IPU_1_OSD_0_STA_ROI_1_SIZE,
	IPU_1_OSD_0_STA_ROI_2_START,
	IPU_1_OSD_0_STA_ROI_2_SIZE,
	IPU_1_OSD_0_STA_ROI_3_START,
	IPU_1_OSD_0_STA_ROI_3_SIZE,
	IPU_1_OSD_0_STA_ROI_4_START,
	IPU_1_OSD_0_STA_ROI_4_SIZE,
	IPU_1_OSD_0_STA_ROI_5_START,
	IPU_1_OSD_0_STA_ROI_5_SIZE,
	IPU_1_OSD_0_STA_ROI_6_START,
	IPU_1_OSD_0_STA_ROI_6_SIZE,
	IPU_1_OSD_0_STA_ROI_7_START,
	IPU_1_OSD_0_STA_ROI_7_SIZE,
	IPU_1_OSD_1_STA_ROI_0_START,
	IPU_1_OSD_1_STA_ROI_0_SIZE,
	IPU_1_OSD_1_STA_ROI_1_START,
	IPU_1_OSD_1_STA_ROI_1_SIZE,
	IPU_1_OSD_1_STA_ROI_2_START,
	IPU_1_OSD_1_STA_ROI_2_SIZE,
	IPU_1_OSD_1_STA_ROI_3_START,
	IPU_1_OSD_1_STA_ROI_3_SIZE,
	IPU_1_OSD_1_STA_ROI_4_START,
	IPU_1_OSD_1_STA_ROI_4_SIZE,
	IPU_1_OSD_1_STA_ROI_5_START,
	IPU_1_OSD_1_STA_ROI_5_SIZE,
	IPU_1_OSD_1_STA_ROI_6_START,
	IPU_1_OSD_1_STA_ROI_6_SIZE,
	IPU_1_OSD_1_STA_ROI_7_START,
	IPU_1_OSD_1_STA_ROI_7_SIZE,
	IPU_1_OSD_2_STA_ROI_0_START,
	IPU_1_OSD_2_STA_ROI_0_SIZE,
	IPU_1_OSD_2_STA_ROI_1_START,
	IPU_1_OSD_2_STA_ROI_1_SIZE,
	IPU_1_OSD_2_STA_ROI_2_START,
	IPU_1_OSD_2_STA_ROI_2_SIZE,
	IPU_1_OSD_2_STA_ROI_3_START,
	IPU_1_OSD_2_STA_ROI_3_SIZE,
	IPU_1_OSD_2_STA_ROI_4_START,
	IPU_1_OSD_2_STA_ROI_4_SIZE,
	IPU_1_OSD_2_STA_ROI_5_START,
	IPU_1_OSD_2_STA_ROI_5_SIZE,
	IPU_1_OSD_2_STA_ROI_6_START,
	IPU_1_OSD_2_STA_ROI_6_SIZE,
	IPU_1_OSD_2_STA_ROI_7_START,
	IPU_1_OSD_2_STA_ROI_7_SIZE,
	IPU_1_OSD_STA_LEVEL,
	IPU_1_OSD_0_ROI_0_ADDR,
	IPU_1_OSD_0_ROI_1_ADDR,
	IPU_1_OSD_0_ROI_2_ADDR,
	IPU_1_OSD_1_ROI_0_ADDR,
	IPU_1_OSD_1_ROI_1_ADDR,
	IPU_1_OSD_1_ROI_2_ADDR,
	IPU_1_OSD_2_ROI_0_ADDR,
	IPU_1_OSD_2_ROI_1_ADDR,
	IPU_1_OSD_2_ROI_2_ADDR,
	IPU_1_US_DDR_STRIDE_LEN_Y,
	IPU_1_US_DDR_STRIDE_LEN_UV,
	IPU_1_DS_0_DDR_STRIDE_LEN_Y,
	IPU_1_DS_0_DDR_STRIDE_LEN_UV,
	IPU_1_DS_1_DDR_STRIDE_LEN_Y,
	IPU_1_DS_1_DDR_STRIDE_LEN_UV,
	IPU_1_DS_2_DDR_STRIDE_LEN_Y,
	IPU_1_DS_2_DDR_STRIDE_LEN_UV,
	IPU_1_DS_3_DDR_STRIDE_LEN_Y,
	IPU_1_DS_3_DDR_STRIDE_LEN_UV,
	IPU_1_DS_4_DDR_STRIDE_LEN_Y,
	IPU_1_DS_4_DDR_STRIDE_LEN_UV,
	/*0x804*/
	IPU_2_SRC_WIDTH,
	IPU_2_SRC_HEIGHT,
	IPU_2_RD_DDR_STRIDE_LEN_Y,
	IPU_2_RD_DDR_STRIDE_LEN_UV,
	IPU_2_US_ROI_EN,
	IPU_2_US_ROI_SIZE,
	IPU_2_DS_0_ROI_EN,
	IPU_2_DS_0_ROI_SIZE,
	IPU_2_DS_1_ROI_EN,
	IPU_2_DS_1_ROI_SIZE,
	IPU_2_DS_2_ROI_EN,
	IPU_2_DS_2_ROI_SIZE,
	IPU_2_DS_3_ROI_EN,
	IPU_2_DS_3_ROI_SIZE,
	IPU_2_DS_4_ROI_EN,
	IPU_2_DS_4_ROI_SIZE,
	IPU_2_US_EN,
	IPU_2_US_STEP,
	IPU_2_DS_0_EN,
	IPU_2_DS_0_STEP,
	IPU_2_DS_1_EN,
	IPU_2_DS_1_STEP,
	IPU_2_DS_2_EN,
	IPU_2_DS_2_STEP,
	IPU_2_DS_3_EN,
	IPU_2_DS_3_STEP,
	IPU_2_DS_4_EN,
	IPU_2_DS_4_STEP,
	IPU_2_OSD_EN,
	IPU_2_OSD_0_ROI_0_START,
	IPU_2_OSD_0_ROI_0_SIZE,
	IPU_2_OSD_0_ROI_1_START,
	IPU_2_OSD_0_ROI_1_SIZE, 
	IPU_2_OSD_0_ROI_2_START,
	IPU_2_OSD_0_ROI_2_SIZE,
	IPU_2_OSD_1_ROI_0_START,
	IPU_2_OSD_1_ROI_0_SIZE,
	IPU_2_OSD_1_ROI_1_START,
	IPU_2_OSD_1_ROI_1_SIZE,
	IPU_2_OSD_1_ROI_2_START,
	IPU_2_OSD_1_ROI_2_SIZE,
	IPU_2_OSD_2_ROI_0_START,
	IPU_2_OSD_2_ROI_0_SIZE,
	IPU_2_OSD_2_ROI_1_START,
	IPU_2_OSD_2_ROI_1_SIZE,
	IPU_2_OSD_2_ROI_2_START,
	IPU_2_OSD_2_ROI_2_SIZE,
	IPU_2_OSD_STA_ENABLE,
	IPU_2_OSD_0_STA_ROI_0_START,
	IPU_2_OSD_0_STA_ROI_0_SIZE,
	IPU_2_OSD_0_STA_ROI_1_START,
	IPU_2_OSD_0_STA_ROI_1_SIZE,
	IPU_2_OSD_0_STA_ROI_2_START,
	IPU_2_OSD_0_STA_ROI_2_SIZE,
	IPU_2_OSD_0_STA_ROI_3_START,
	IPU_2_OSD_0_STA_ROI_3_SIZE,
	IPU_2_OSD_0_STA_ROI_4_START,
	IPU_2_OSD_0_STA_ROI_4_SIZE,
	IPU_2_OSD_0_STA_ROI_5_START,
	IPU_2_OSD_0_STA_ROI_5_SIZE,
	IPU_2_OSD_0_STA_ROI_6_START,
	IPU_2_OSD_0_STA_ROI_6_SIZE,
	IPU_2_OSD_0_STA_ROI_7_START,
	IPU_2_OSD_0_STA_ROI_7_SIZE,
	IPU_2_OSD_1_STA_ROI_0_START,
	IPU_2_OSD_1_STA_ROI_0_SIZE,
	IPU_2_OSD_1_STA_ROI_1_START,
	IPU_2_OSD_1_STA_ROI_1_SIZE,
	IPU_2_OSD_1_STA_ROI_2_START,
	IPU_2_OSD_1_STA_ROI_2_SIZE,
	IPU_2_OSD_1_STA_ROI_3_START,
	IPU_2_OSD_1_STA_ROI_3_SIZE,
	IPU_2_OSD_1_STA_ROI_4_START,
	IPU_2_OSD_1_STA_ROI_4_SIZE,
	IPU_2_OSD_1_STA_ROI_5_START,
	IPU_2_OSD_1_STA_ROI_5_SIZE,
	IPU_2_OSD_1_STA_ROI_6_START,
	IPU_2_OSD_1_STA_ROI_6_SIZE,
	IPU_2_OSD_1_STA_ROI_7_START,
	IPU_2_OSD_1_STA_ROI_7_SIZE,
	IPU_2_OSD_2_STA_ROI_0_START,
	IPU_2_OSD_2_STA_ROI_0_SIZE,
	IPU_2_OSD_2_STA_ROI_1_START,
	IPU_2_OSD_2_STA_ROI_1_SIZE,
	IPU_2_OSD_2_STA_ROI_2_START,
	IPU_2_OSD_2_STA_ROI_2_SIZE,
	IPU_2_OSD_2_STA_ROI_3_START,
	IPU_2_OSD_2_STA_ROI_3_SIZE,
	IPU_2_OSD_2_STA_ROI_4_START,
	IPU_2_OSD_2_STA_ROI_4_SIZE,
	IPU_2_OSD_2_STA_ROI_5_START,
	IPU_2_OSD_2_STA_ROI_5_SIZE,
	IPU_2_OSD_2_STA_ROI_6_START,
	IPU_2_OSD_2_STA_ROI_6_SIZE,
	IPU_2_OSD_2_STA_ROI_7_START,
	IPU_2_OSD_2_STA_ROI_7_SIZE,
	IPU_2_OSD_STA_LEVEL,
	IPU_2_OSD_0_ROI_0_ADDR,
	IPU_2_OSD_0_ROI_1_ADDR,
	IPU_2_OSD_0_ROI_2_ADDR,
	IPU_2_OSD_1_ROI_0_ADDR,
	IPU_2_OSD_1_ROI_1_ADDR,
	IPU_2_OSD_1_ROI_2_ADDR,
	IPU_2_OSD_2_ROI_0_ADDR,
	IPU_2_OSD_2_ROI_1_ADDR,
	IPU_2_OSD_2_ROI_2_ADDR,
	IPU_2_US_DDR_STRIDE_LEN_Y,
	IPU_2_US_DDR_STRIDE_LEN_UV,
	IPU_2_DS_0_DDR_STRIDE_LEN_Y,
	IPU_2_DS_0_DDR_STRIDE_LEN_UV,
	IPU_2_DS_1_DDR_STRIDE_LEN_Y,
	IPU_2_DS_1_DDR_STRIDE_LEN_UV,
	IPU_2_DS_2_DDR_STRIDE_LEN_Y,
	IPU_2_DS_2_DDR_STRIDE_LEN_UV,
	IPU_2_DS_3_DDR_STRIDE_LEN_Y,
	IPU_2_DS_3_DDR_STRIDE_LEN_UV,
	IPU_2_DS_4_DDR_STRIDE_LEN_Y,
	IPU_2_DS_4_DDR_STRIDE_LEN_UV,
	/*0xc04*/
	IPU_3_SRC_WIDTH,
	IPU_3_SRC_HEIGHT,
	IPU_3_RD_DDR_STRIDE_LEN_Y,
	IPU_3_RD_DDR_STRIDE_LEN_UV,
	IPU_3_US_ROI_EN,
	IPU_3_US_ROI_SIZE,
	IPU_3_DS_0_ROI_EN,
	IPU_3_DS_0_ROI_SIZE,
	IPU_3_DS_1_ROI_EN,
	IPU_3_DS_1_ROI_SIZE,
	IPU_3_DS_2_ROI_EN,
	IPU_3_DS_2_ROI_SIZE,
	IPU_3_DS_3_ROI_EN,
	IPU_3_DS_3_ROI_SIZE,
	IPU_3_DS_4_ROI_EN,
	IPU_3_DS_4_ROI_SIZE,
	IPU_3_US_EN,
	IPU_3_US_STEP,
	IPU_3_DS_0_EN,
	IPU_3_DS_0_STEP,
	IPU_3_DS_1_EN,
	IPU_3_DS_1_STEP,
	IPU_3_DS_2_EN,
	IPU_3_DS_2_STEP,
	IPU_3_DS_3_EN,
	IPU_3_DS_3_STEP,
	IPU_3_DS_4_EN,
	IPU_3_DS_4_STEP,
	IPU_3_OSD_EN,
	IPU_3_OSD_0_ROI_0_START,
	IPU_3_OSD_0_ROI_0_SIZE,
	IPU_3_OSD_0_ROI_1_START,
	IPU_3_OSD_0_ROI_1_SIZE, 
	IPU_3_OSD_0_ROI_2_START,
	IPU_3_OSD_0_ROI_2_SIZE,
	IPU_3_OSD_1_ROI_0_START,
	IPU_3_OSD_1_ROI_0_SIZE,
	IPU_3_OSD_1_ROI_1_START,
	IPU_3_OSD_1_ROI_1_SIZE,
	IPU_3_OSD_1_ROI_2_START,
	IPU_3_OSD_1_ROI_2_SIZE,
	IPU_3_OSD_2_ROI_0_START,
	IPU_3_OSD_2_ROI_0_SIZE,
	IPU_3_OSD_2_ROI_1_START,
	IPU_3_OSD_2_ROI_1_SIZE,
	IPU_3_OSD_2_ROI_2_START,
	IPU_3_OSD_2_ROI_2_SIZE,
	IPU_3_OSD_STA_ENABLE,
	IPU_3_OSD_0_STA_ROI_0_START,
	IPU_3_OSD_0_STA_ROI_0_SIZE,
	IPU_3_OSD_0_STA_ROI_1_START,
	IPU_3_OSD_0_STA_ROI_1_SIZE,
	IPU_3_OSD_0_STA_ROI_2_START,
	IPU_3_OSD_0_STA_ROI_2_SIZE,
	IPU_3_OSD_0_STA_ROI_3_START,
	IPU_3_OSD_0_STA_ROI_3_SIZE,
	IPU_3_OSD_0_STA_ROI_4_START,
	IPU_3_OSD_0_STA_ROI_4_SIZE,
	IPU_3_OSD_0_STA_ROI_5_START,
	IPU_3_OSD_0_STA_ROI_5_SIZE,
	IPU_3_OSD_0_STA_ROI_6_START,
	IPU_3_OSD_0_STA_ROI_6_SIZE,
	IPU_3_OSD_0_STA_ROI_7_START,
	IPU_3_OSD_0_STA_ROI_7_SIZE,
	IPU_3_OSD_1_STA_ROI_0_START,
	IPU_3_OSD_1_STA_ROI_0_SIZE,
	IPU_3_OSD_1_STA_ROI_1_START,
	IPU_3_OSD_1_STA_ROI_1_SIZE,
	IPU_3_OSD_1_STA_ROI_2_START,
	IPU_3_OSD_1_STA_ROI_2_SIZE,
	IPU_3_OSD_1_STA_ROI_3_START,
	IPU_3_OSD_1_STA_ROI_3_SIZE,
	IPU_3_OSD_1_STA_ROI_4_START,
	IPU_3_OSD_1_STA_ROI_4_SIZE,
	IPU_3_OSD_1_STA_ROI_5_START,
	IPU_3_OSD_1_STA_ROI_5_SIZE,
	IPU_3_OSD_1_STA_ROI_6_START,
	IPU_3_OSD_1_STA_ROI_6_SIZE,
	IPU_3_OSD_1_STA_ROI_7_START,
	IPU_3_OSD_1_STA_ROI_7_SIZE,
	IPU_3_OSD_2_STA_ROI_0_START,
	IPU_3_OSD_2_STA_ROI_0_SIZE,
	IPU_3_OSD_2_STA_ROI_1_START,
	IPU_3_OSD_2_STA_ROI_1_SIZE,
	IPU_3_OSD_2_STA_ROI_2_START,
	IPU_3_OSD_2_STA_ROI_2_SIZE,
	IPU_3_OSD_2_STA_ROI_3_START,
	IPU_3_OSD_2_STA_ROI_3_SIZE,
	IPU_3_OSD_2_STA_ROI_4_START,
	IPU_3_OSD_2_STA_ROI_4_SIZE,
	IPU_3_OSD_2_STA_ROI_5_START,
	IPU_3_OSD_2_STA_ROI_5_SIZE,
	IPU_3_OSD_2_STA_ROI_6_START,
	IPU_3_OSD_2_STA_ROI_6_SIZE,
	IPU_3_OSD_2_STA_ROI_7_START,
	IPU_3_OSD_2_STA_ROI_7_SIZE,
	IPU_3_OSD_STA_LEVEL,
	IPU_3_OSD_0_ROI_0_ADDR,
	IPU_3_OSD_0_ROI_1_ADDR,
	IPU_3_OSD_0_ROI_2_ADDR,
	IPU_3_OSD_1_ROI_0_ADDR,
	IPU_3_OSD_1_ROI_1_ADDR,
	IPU_3_OSD_1_ROI_2_ADDR,
	IPU_3_OSD_2_ROI_0_ADDR,
	IPU_3_OSD_2_ROI_1_ADDR,
	IPU_3_OSD_2_ROI_2_ADDR,
	IPU_3_US_DDR_STRIDE_LEN_Y,
	IPU_3_US_DDR_STRIDE_LEN_UV,
	IPU_3_DS_0_DDR_STRIDE_LEN_Y,
	IPU_3_DS_0_DDR_STRIDE_LEN_UV,
	IPU_3_DS_1_DDR_STRIDE_LEN_Y,
	IPU_3_DS_1_DDR_STRIDE_LEN_UV,
	IPU_3_DS_2_DDR_STRIDE_LEN_Y,
	IPU_3_DS_2_DDR_STRIDE_LEN_UV,
	IPU_3_DS_3_DDR_STRIDE_LEN_Y,
	IPU_3_DS_3_DDR_STRIDE_LEN_UV,
	IPU_3_DS_4_DDR_STRIDE_LEN_Y,
	IPU_3_DS_4_DDR_STRIDE_LEN_UV,
	/*0xE50*/
	IPU_INT_MASK,
	IPU_INT_STATUS,
	IPU_CFG_RDY,
	IPU_CFG_SEL,
	IPU_BUS_CFG,
	IPU_BUS_CTRL_WM_0,
	IPU_BUS_CTRL_WM_1,
	IPU_BUS_CTRL_WM_2,
	IPU_BUS_CTRL_WM_3,
	IPU_BUS_CTRL_WM_4,
	IPU_BUS_CTRL_WM_5,
	IPU_BUS_CTRL_WM_6,
	IPU_BUS_CTRL_WM_7,
	IPU_BUS_CTRL_WM_8,
	IPU_BUS_CTRL_WM_9,
	IPU_BUS_CTRL_WM_10,
	IPU_BUS_CTRL_WM_11,
	IPU_BUS_CTRL_WM_12,
	IPU_BUS_CTRL_RM_0,
	IPU_BUS_CTRL_RM_1,
	IPU_BUS_CTRL_RM_2,
	IPU_BUS_CTRL_RM_3,
	IPU_BUS_CTRL_RM_4,
	IPU_FRAME_ID,
	IPU_OSD_COLOR_0,
	IPU_OSD_COLOR_1,
	IPU_OSD_COLOR_2,
	IPU_OSD_COLOR_3,
	IPU_OSD_COLOR_4,
	IPU_OSD_COLOR_5,
	IPU_OSD_COLOR_6,
	IPU_OSD_COLOR_7,
	IPU_OSD_COLOR_8,
	IPU_OSD_COLOR_9,
	IPU_OSD_COLOR_10,
	IPU_OSD_COLOR_11,
	IPU_OSD_COLOR_12,
	IPU_OSD_COLOR_13,
	IPU_OSD_COLOR_14,
	IPU_CFG,
	IPU_RD_DDR_ADDR_Y,
	IPU_RD_DDR_ADDR_UV,
	IPU_US_DDR_Y,
	IPU_US_DDR_UV,
	IPU_DS_0_DDR_Y,
	IPU_DS_0_DDR_UV,
	IPU_DS_1_DDR_Y,
	IPU_DS_1_DDR_UV,
	IPU_DS_2_DDR_Y,
	IPU_DS_2_DDR_UV,
	IPU_DS_3_DDR_Y,
	IPU_DS_3_DDR_UV,
	IPU_DS_4_DDR_Y,
	IPU_DS_4_DDR_UV,
	IPU_OSD_0_STA_0_BIN01,
	IPU_OSD_0_STA_0_BIN23,
	IPU_OSD_0_STA_1_BIN01,
	IPU_OSD_0_STA_1_BIN23,
	IPU_OSD_0_STA_2_BIN01,
	IPU_OSD_0_STA_2_BIN23,
	IPU_OSD_0_STA_3_BIN01,
	IPU_OSD_0_STA_3_BIN23,
	IPU_OSD_0_STA_4_BIN01,
	IPU_OSD_0_STA_4_BIN23,
	IPU_OSD_0_STA_5_BIN01,
	IPU_OSD_0_STA_5_BIN23,
	IPU_OSD_0_STA_6_BIN01,
	IPU_OSD_0_STA_6_BIN23,
	IPU_OSD_0_STA_7_BIN01,
	IPU_OSD_0_STA_7_BIN23,
	IPU_OSD_1_STA_0_BIN01,
	IPU_OSD_1_STA_0_BIN23,
	IPU_OSD_1_STA_1_BIN01,
	IPU_OSD_1_STA_1_BIN23,
	IPU_OSD_1_STA_2_BIN01,
	IPU_OSD_1_STA_2_BIN23,
	IPU_OSD_1_STA_3_BIN01,
	IPU_OSD_1_STA_3_BIN23,
	IPU_OSD_1_STA_4_BIN01,
	IPU_OSD_1_STA_4_BIN23,
	IPU_OSD_1_STA_5_BIN01,
	IPU_OSD_1_STA_5_BIN23,
	IPU_OSD_1_STA_6_BIN01,
	IPU_OSD_1_STA_6_BIN23,
	IPU_OSD_1_STA_7_BIN01,
	IPU_OSD_1_STA_7_BIN23,
	IPU_OSD_2_STA_0_BIN01,
	IPU_OSD_2_STA_0_BIN23,
	IPU_OSD_2_STA_1_BIN01,
	IPU_OSD_2_STA_1_BIN23,
	IPU_OSD_2_STA_2_BIN01,
	IPU_OSD_2_STA_2_BIN23,
	IPU_OSD_2_STA_3_BIN01,
	IPU_OSD_2_STA_3_BIN23,
	IPU_OSD_2_STA_4_BIN01,
	IPU_OSD_2_STA_4_BIN23,
	IPU_OSD_2_STA_5_BIN01,
	IPU_OSD_2_STA_5_BIN23,
	IPU_OSD_2_STA_6_BIN01,
	IPU_OSD_2_STA_6_BIN23,
	IPU_OSD_2_STA_7_BIN01,
	IPU_OSD_2_STA_7_BIN23,
	IPU_DDR_START,
	IPU_TEST_Y_SET, 
	IPU_TEST_U_SET,
	IPU_TEST_V_SET,
	IPU_PRE_INT_SET,
	NUM_OF_IPU_REG,
};

static struct vio_reg_def ipu_regs[NUM_OF_IPU_REG]={
	{"IPU_0_SRC_WIDTH",             0x0004, RW},
	{"IPU_0_SRC_HEIGHT",            0x0008, RW},
	{"IPU_0_RD_DDR_STRIDE_LEN_Y",   0x000C, RW},
	{"IPU_0_RD_DDR_STRIDE_LEN_UV",  0x0010, RW},
	{"IPU_0_US_ROI_EN",             0x0014, RW},
	{"IPU_0_US_ROI_SIZE",           0x0018, RW},
	{"IPU_0_DS_0_ROI_EN",           0x001C, RW},
	{"IPU_0_DS_0_ROI_SIZE",         0x0020, RW},
	{"IPU_0_DS_1_ROI_EN",           0x0024, RW},
	{"IPU_0_DS_1_ROI_SIZE",         0x0028, RW},
	{"IPU_0_DS_2_ROI_EN",           0x002C, RW},
	{"IPU_0_DS_2_ROI_SIZE",         0x0030, RW},
	{"IPU_0_DS_3_ROI_EN",           0x0034, RW},
	{"IPU_0_DS_3_ROI_SIZE",         0x0038, RW},
	{"IPU_0_DS_4_ROI_EN",           0x003C, RW},
	{"IPU_0_DS_4_ROI_SIZE",         0x0040, RW},
	{"IPU_0_US_EN",                 0x0044, RW},
	{"IPU_0_US_STEP",               0x0048, RW},
	{"IPU_0_DS_0_EN",               0x004C, RW},
	{"IPU_0_DS_0_STEP",             0x0050, RW},
	{"IPU_0_DS_1_EN",               0x0054, RW},
	{"IPU_0_DS_1_STEP",             0x0058, RW},
	{"IPU_0_DS_2_EN",               0x005C, RW},
	{"IPU_0_DS_2_STEP",             0x0060, RW},
	{"IPU_0_DS_3_EN",               0x0064, RW},
	{"IPU_0_DS_3_STEP",             0x0068, RW},
	{"IPU_0_DS_4_EN",               0x006C, RW},
	{"IPU_0_DS_4_STEP",             0x0070, RW},
	{"IPU_0_OSD_EN",                0x0074, RW},
	{"IPU_0_OSD_0_ROI_0_START",     0x0078, RW},
	{"IPU_0_OSD_0_ROI_0_SIZE",      0x007C, RW},
	{"IPU_0_OSD_0_ROI_1_START",     0x0080, RW},
	{"IPU_0_OSD_0_ROI_1_SIZE",      0x0084, RW},
	{"IPU_0_OSD_0_ROI_2_START",     0x0088, RW},
	{"IPU_0_OSD_0_ROI_2_SIZE",      0x008C, RW},
	{"IPU_0_OSD_1_ROI_0_START",     0x0090, RW},
	{"IPU_0_OSD_1_ROI_0_SIZE",      0x0094, RW},
	{"IPU_0_OSD_1_ROI_1_START",     0x0098, RW},
	{"IPU_0_OSD_1_ROI_1_SIZE",      0x009C, RW},
	{"IPU_0_OSD_1_ROI_2_START",     0x00A0, RW},
	{"IPU_0_OSD_1_ROI_2_SIZE",      0x00A4, RW},
	{"IPU_0_OSD_2_ROI_0_START",     0x00A8, RW},
	{"IPU_0_OSD_2_ROI_0_SIZE",      0x00AC, RW},
	{"IPU_0_OSD_2_ROI_1_START",     0x00B0, RW},
	{"IPU_0_OSD_2_ROI_1_SIZE",      0x00B4, RW},
	{"IPU_0_OSD_2_ROI_2_START",     0x00B8, RW},
	{"IPU_0_OSD_2_ROI_2_SIZE",      0x00BC, RW},
	{"IPU_0_OSD_STA_ENABLE",        0x00C0, RW},
	{"IPU_0_OSD_0_STA_ROI_0_START", 0x00C4, RW},
	{"IPU_0_OSD_0_STA_ROI_0_SIZE",  0x00C8, RW},
	{"IPU_0_OSD_0_STA_ROI_1_START", 0x00CC, RW},
	{"IPU_0_OSD_0_STA_ROI_1_SIZE",  0x00D0, RW},
	{"IPU_0_OSD_0_STA_ROI_2_START", 0x00D4, RW},
	{"IPU_0_OSD_0_STA_ROI_2_SIZE",  0x00D8, RW},
	{"IPU_0_OSD_0_STA_ROI_3_START", 0x00DC, RW},
	{"IPU_0_OSD_0_STA_ROI_3_SIZE",  0x00E0, RW},
	{"IPU_0_OSD_0_STA_ROI_4_START", 0x00E4, RW},
	{"IPU_0_OSD_0_STA_ROI_4_SIZE",  0x00E8, RW},
	{"IPU_0_OSD_0_STA_ROI_5_START", 0x00EC, RW},
	{"IPU_0_OSD_0_STA_ROI_5_SIZE",  0x00F0, RW},
	{"IPU_0_OSD_0_STA_ROI_6_START", 0x00F4, RW},
	{"IPU_0_OSD_0_STA_ROI_6_SIZE",  0x00F8, RW},
	{"IPU_0_OSD_0_STA_ROI_7_START", 0x00FC, RW},
	{"IPU_0_OSD_0_STA_ROI_7_SIZE",  0x0100, RW},
	{"IPU_0_OSD_1_STA_ROI_0_START", 0x0104, RW},
	{"IPU_0_OSD_1_STA_ROI_0_SIZE",  0x0108, RW},
	{"IPU_0_OSD_1_STA_ROI_1_START", 0x010C, RW},
	{"IPU_0_OSD_1_STA_ROI_1_SIZE",  0x0110, RW},
	{"IPU_0_OSD_1_STA_ROI_2_START", 0x0114, RW},
	{"IPU_0_OSD_1_STA_ROI_2_SIZE",  0x0118, RW},
	{"IPU_0_OSD_1_STA_ROI_3_START", 0x011C, RW},
	{"IPU_0_OSD_1_STA_ROI_3_SIZE",  0x0120, RW},
	{"IPU_0_OSD_1_STA_ROI_4_START", 0x0124, RW},
	{"IPU_0_OSD_1_STA_ROI_4_SIZE",  0x0128, RW},
	{"IPU_0_OSD_1_STA_ROI_5_START", 0x012C, RW},
	{"IPU_0_OSD_1_STA_ROI_5_SIZE",  0x0130, RW},
	{"IPU_0_OSD_1_STA_ROI_6_START", 0x0134, RW},
	{"IPU_0_OSD_1_STA_ROI_6_SIZE",  0x0138, RW},
	{"IPU_0_OSD_1_STA_ROI_7_START", 0x013C, RW},
	{"IPU_0_OSD_1_STA_ROI_7_SIZE",  0x0140, RW},
	{"IPU_0_OSD_2_STA_ROI_0_START", 0x0144, RW},
	{"IPU_0_OSD_2_STA_ROI_0_SIZE",  0x0148, RW},
	{"IPU_0_OSD_2_STA_ROI_1_START", 0x014C, RW},
	{"IPU_0_OSD_2_STA_ROI_1_SIZE",  0x0150, RW},
	{"IPU_0_OSD_2_STA_ROI_2_START", 0x0154, RW},
	{"IPU_0_OSD_2_STA_ROI_2_SIZE",  0x0158, RW},
	{"IPU_0_OSD_2_STA_ROI_3_START", 0x015C, RW},
	{"IPU_0_OSD_2_STA_ROI_3_SIZE",  0x0160, RW},
	{"IPU_0_OSD_2_STA_ROI_4_START", 0x0164, RW},
	{"IPU_0_OSD_2_STA_ROI_4_SIZE",  0x0168, RW},
	{"IPU_0_OSD_2_STA_ROI_5_START", 0x016C, RW},
	{"IPU_0_OSD_2_STA_ROI_5_SIZE",  0x0170, RW},
	{"IPU_0_OSD_2_STA_ROI_6_START", 0x0174, RW},
	{"IPU_0_OSD_2_STA_ROI_6_SIZE",  0x0178, RW},
	{"IPU_0_OSD_2_STA_ROI_7_START", 0x017C, RW},
	{"IPU_0_OSD_2_STA_ROI_7_SIZE",  0x0180, RW},
	{"IPU_0_OSD_STA_LEVEL",         0x0184, RW},
	{"IPU_0_OSD_0_ROI_0_ADDR",      0x0188, RW},
	{"IPU_0_OSD_0_ROI_1_ADDR",      0x018C, RW},
	{"IPU_0_OSD_0_ROI_2_ADDR",      0x0190, RW},
	{"IPU_0_OSD_1_ROI_0_ADDR",      0x0194, RW},
	{"IPU_0_OSD_1_ROI_1_ADDR",      0x0198, RW},
	{"IPU_0_OSD_1_ROI_2_ADDR",      0x019C, RW},
	{"IPU_0_OSD_2_ROI_0_ADDR",      0x01A0, RW},
	{"IPU_0_OSD_2_ROI_1_ADDR",      0x01A4, RW},
	{"IPU_0_OSD_2_ROI_2_ADDR",      0x01A8, RW},
	{"IPU_0_US_DDR_STRIDE_LEN_Y",   0x01B8, RW},
	{"IPU_0_US_DDR_STRIDE_LEN_UV",  0x01BC, RW},
	{"IPU_0_DS_0_DDR_STRIDE_LEN_Y", 0x01C0, RW},
	{"IPU_0_DS_0_DDR_STRIDE_LEN_UV",0x01C4, RW},
	{"IPU_0_DS_1_DDR_STRIDE_LEN_Y", 0x01C8, RW},
	{"IPU_0_DS_1_DDR_STRIDE_LEN_UV",0x01CC, RW},
	{"IPU_0_DS_2_DDR_STRIDE_LEN_Y", 0x01D0, RW},
	{"IPU_0_DS_2_DDR_STRIDE_LEN_UV",0x01D4, RW},
	{"IPU_0_DS_3_DDR_STRIDE_LEN_Y", 0x01D8, RW},
	{"IPU_0_DS_3_DDR_STRIDE_LEN_UV",0x01DC, RW},
	{"IPU_0_DS_4_DDR_STRIDE_LEN_Y", 0x01E0, RW},
	{"IPU_0_DS_4_DDR_STRIDE_LEN_UV",0x01E4, RW},
	{"IPU_SIZE_ERR",                0x0200, RW},
	{"IPU_CHECKSUM_Y",              0x0204, RW},
	{"IPU_CHECKSUM_UY",             0x0208, RW},
	{"IPU_SCALE_STATE",             0x020C, RW},
	{"IPU_LAYER_0_WR_RD_LINE_CNT",  0x0210, RW},
	{"IPU_LAYER_1_WR_RD_LINE_CNT",  0x0214, RW},
	{"IPU_LAYER_2_WR_RD_LINE_CNT",  0x0218, RW},
	{"IPU_LAYER_0_REQ_LINE_CNT",    0x021C, RW},
	{"IPU_LAYER_1_REQ_LINE_CNT",    0x0220, RW},
	{"IPU_LAYER_2_REQ_LINE_CNT",    0x0224, RW},
	{"IPU_ERR_CLR",                 0x0228, RW},
	{"IPU_ERR_STATUS",              0x022C, RW},
	{"IPU_WR_DDR_FIFO_THRED_0", 	0x0230, RW},
	{"IPU_WR_DDR_FIFO_THRED_1",     0x0234, RW},
	/*0x404*/
	{"IPU_1_SRC_WIDTH",             0x0404, RW},
	{"IPU_1_SRC_HEIGHT",            0x0408, RW},
	{"IPU_1_RD_DDR_STRIDE_LEN_Y",   0x040C, RW},
	{"IPU_1_RD_DDR_STRIDE_LEN_UV",  0x0410, RW},
	{"IPU_1_US_ROI_EN",             0x0414, RW},
	{"IPU_1_US_ROI_SIZE",           0x0418, RW},
	{"IPU_1_DS_0_ROI_EN",           0x041C, RW},
	{"IPU_1_DS_0_ROI_SIZE",         0x0420, RW},
	{"IPU_1_DS_1_ROI_EN",           0x0424, RW},
	{"IPU_1_DS_1_ROI_SIZE",         0x0428, RW},
	{"IPU_1_DS_2_ROI_EN",           0x042C, RW},
	{"IPU_1_DS_2_ROI_SIZE",         0x0430, RW},
	{"IPU_1_DS_3_ROI_EN",           0x0434, RW},
	{"IPU_1_DS_3_ROI_SIZE",         0x0438, RW},
	{"IPU_1_DS_4_ROI_EN",           0x043C, RW},
	{"IPU_1_DS_4_ROI_SIZE",         0x0440, RW},
	{"IPU_1_US_EN",                 0x0444, RW},
	{"IPU_1_US_STEP",               0x0448, RW},
	{"IPU_1_DS_0_EN",               0x044C, RW},
	{"IPU_1_DS_0_STEP",             0x0450, RW},
	{"IPU_1_DS_1_EN",               0x0454, RW},
	{"IPU_1_DS_1_STEP",             0x0458, RW},
	{"IPU_1_DS_2_EN",               0x045C, RW},
	{"IPU_1_DS_2_STEP",             0x0460, RW},
	{"IPU_1_DS_3_EN",               0x0464, RW},
	{"IPU_1_DS_3_STEP",             0x0468, RW},
	{"IPU_1_DS_4_EN",               0x046C, RW},
	{"IPU_1_DS_4_STEP",             0x0470, RW},
	{"IPU_1_OSD_EN",                0x0474, RW},
	{"IPU_1_OSD_0_ROI_0_START",     0x0478, RW},
	{"IPU_1_OSD_0_ROI_0_SIZE",      0x047C, RW},
	{"IPU_1_OSD_0_ROI_1_START",     0x0480, RW},
	{"IPU_1_OSD_0_ROI_1_SIZE",      0x0484, RW},
	{"IPU_1_OSD_0_ROI_2_START",     0x0488, RW},
	{"IPU_1_OSD_0_ROI_2_SIZE",      0x048C, RW},
	{"IPU_1_OSD_1_ROI_0_START",     0x0490, RW},
	{"IPU_1_OSD_1_ROI_0_SIZE",      0x0494, RW},
	{"IPU_1_OSD_1_ROI_1_START",     0x0498, RW},
	{"IPU_1_OSD_1_ROI_1_SIZE",      0x049C, RW},
	{"IPU_1_OSD_1_ROI_2_START",     0x04A0, RW},
	{"IPU_1_OSD_1_ROI_2_SIZE",      0x04A4, RW},
	{"IPU_1_OSD_2_ROI_0_START",     0x04A8, RW},
	{"IPU_1_OSD_2_ROI_0_SIZE",      0x04AC, RW},
	{"IPU_1_OSD_2_ROI_1_START",     0x04B0, RW},
	{"IPU_1_OSD_2_ROI_1_SIZE",      0x04B4, RW},
	{"IPU_1_OSD_2_ROI_2_START",     0x04B8, RW},
	{"IPU_1_OSD_2_ROI_2_SIZE",      0x04BC, RW},
	{"IPU_1_OSD_STA_ENABLE",        0x04C0, RW},
	{"IPU_1_OSD_0_STA_ROI_0_START", 0x04C4, RW},
	{"IPU_1_OSD_0_STA_ROI_0_SIZE",  0x04C8, RW},
	{"IPU_1_OSD_0_STA_ROI_1_START", 0x04CC, RW},
	{"IPU_1_OSD_0_STA_ROI_1_SIZE",  0x04D0, RW},
	{"IPU_1_OSD_0_STA_ROI_2_START", 0x04D4, RW},
	{"IPU_1_OSD_0_STA_ROI_2_SIZE",  0x04D8, RW},
	{"IPU_1_OSD_0_STA_ROI_3_START", 0x04DC, RW},
	{"IPU_1_OSD_0_STA_ROI_3_SIZE",  0x04E0, RW},
	{"IPU_1_OSD_0_STA_ROI_4_START", 0x04E4, RW},
	{"IPU_1_OSD_0_STA_ROI_4_SIZE",  0x04E8, RW},
	{"IPU_1_OSD_0_STA_ROI_5_START", 0x04EC, RW},
	{"IPU_1_OSD_0_STA_ROI_5_SIZE",  0x04F0, RW},
	{"IPU_1_OSD_0_STA_ROI_6_START", 0x04F4, RW},
	{"IPU_1_OSD_0_STA_ROI_6_SIZE",  0x04F8, RW},
	{"IPU_1_OSD_0_STA_ROI_7_START", 0x04FC, RW},
	{"IPU_1_OSD_0_STA_ROI_7_SIZE",  0x0500, RW},
	{"IPU_1_OSD_1_STA_ROI_0_START", 0x0504, RW},
	{"IPU_1_OSD_1_STA_ROI_0_SIZE",  0x0508, RW},
	{"IPU_1_OSD_1_STA_ROI_1_START", 0x050C, RW},
	{"IPU_1_OSD_1_STA_ROI_1_SIZE",  0x0510, RW},
	{"IPU_1_OSD_1_STA_ROI_2_START", 0x0514, RW},
	{"IPU_1_OSD_1_STA_ROI_2_SIZE",  0x0518, RW},
	{"IPU_1_OSD_1_STA_ROI_3_START", 0x051C, RW},
	{"IPU_1_OSD_1_STA_ROI_3_SIZE",  0x0520, RW},
	{"IPU_1_OSD_1_STA_ROI_4_START", 0x0524, RW},
	{"IPU_1_OSD_1_STA_ROI_4_SIZE",  0x0528, RW},
	{"IPU_1_OSD_1_STA_ROI_5_START", 0x052C, RW},
	{"IPU_1_OSD_1_STA_ROI_5_SIZE",  0x0530, RW},
	{"IPU_1_OSD_1_STA_ROI_6_START", 0x0534, RW},
	{"IPU_1_OSD_1_STA_ROI_6_SIZE",  0x0538, RW},
	{"IPU_1_OSD_1_STA_ROI_7_START", 0x053C, RW},
	{"IPU_1_OSD_1_STA_ROI_7_SIZE",  0x0540, RW},
	{"IPU_1_OSD_2_STA_ROI_0_START", 0x0544, RW},
	{"IPU_1_OSD_2_STA_ROI_0_SIZE",  0x0548, RW},
	{"IPU_1_OSD_2_STA_ROI_1_START", 0x054C, RW},
	{"IPU_1_OSD_2_STA_ROI_1_SIZE",  0x0550, RW},
	{"IPU_1_OSD_2_STA_ROI_2_START", 0x0554, RW},
	{"IPU_1_OSD_2_STA_ROI_2_SIZE",  0x0558, RW},
	{"IPU_1_OSD_2_STA_ROI_3_START", 0x055C, RW},
	{"IPU_1_OSD_2_STA_ROI_3_SIZE",  0x0560, RW},
	{"IPU_1_OSD_2_STA_ROI_4_START", 0x0564, RW},
	{"IPU_1_OSD_2_STA_ROI_4_SIZE",  0x0568, RW},
	{"IPU_1_OSD_2_STA_ROI_5_START", 0x056C, RW},
	{"IPU_1_OSD_2_STA_ROI_5_SIZE",  0x0570, RW},
	{"IPU_1_OSD_2_STA_ROI_6_START", 0x0574, RW},
	{"IPU_1_OSD_2_STA_ROI_6_SIZE",  0x0578, RW},
	{"IPU_1_OSD_2_STA_ROI_7_START", 0x057C, RW},
	{"IPU_1_OSD_2_STA_ROI_7_SIZE",  0x0580, RW},
	{"IPU_1_OSD_STA_LEVEL",         0x0584, RW},
	{"IPU_1_OSD_0_ROI_0_ADDR",      0x0588, RW},
	{"IPU_1_OSD_0_ROI_1_ADDR",      0x058C, RW},
	{"IPU_1_OSD_0_ROI_2_ADDR",      0x0590, RW},
	{"IPU_1_OSD_1_ROI_0_ADDR",      0x0594, RW},
	{"IPU_1_OSD_1_ROI_1_ADDR",      0x0598, RW},
	{"IPU_1_OSD_1_ROI_2_ADDR",      0x059C, RW},
	{"IPU_1_OSD_2_ROI_0_ADDR",      0x05A0, RW},
	{"IPU_1_OSD_2_ROI_1_ADDR",      0x05A4, RW},
	{"IPU_1_OSD_2_ROI_2_ADDR",      0x05A8, RW},
	{"IPU_1_US_DDR_STRIDE_LEN_Y",   0x05B8, RW},
	{"IPU_1_US_DDR_STRIDE_LEN_UV",  0x05BC, RW},
	{"IPU_1_DS_0_DDR_STRIDE_LEN_Y", 0x05C0, RW},
	{"IPU_1_DS_0_DDR_STRIDE_LEN_UV",0x05C4, RW},
	{"IPU_1_DS_1_DDR_STRIDE_LEN_Y", 0x05C8, RW},
	{"IPU_1_DS_1_DDR_STRIDE_LEN_UV",0x05CC, RW},
	{"IPU_1_DS_2_DDR_STRIDE_LEN_Y", 0x05D0, RW},
	{"IPU_1_DS_2_DDR_STRIDE_LEN_UV",0x05D4, RW},
	{"IPU_1_DS_3_DDR_STRIDE_LEN_Y", 0x05D8, RW},
	{"IPU_1_DS_3_DDR_STRIDE_LEN_UV",0x05DC, RW},
	{"IPU_1_DS_4_DDR_STRIDE_LEN_Y", 0x05E0, RW},
	{"IPU_1_DS_4_DDR_STRIDE_LEN_UV",0x05E4, RW},
	/*0x804*/
	{"IPU_2_SRC_WIDTH",             0x0804, RW},
	{"IPU_2_SRC_HEIGHT",            0x0808, RW},
	{"IPU_2_RD_DDR_STRIDE_LEN_Y",   0x080C, RW},
	{"IPU_2_RD_DDR_STRIDE_LEN_UV",  0x0810, RW},
	{"IPU_2_US_ROI_EN",             0x0814, RW},
	{"IPU_2_US_ROI_SIZE",           0x0818, RW},
	{"IPU_2_DS_0_ROI_EN",           0x081C, RW},
	{"IPU_2_DS_0_ROI_SIZE",         0x0820, RW},
	{"IPU_2_DS_1_ROI_EN",           0x0824, RW},
	{"IPU_2_DS_1_ROI_SIZE",         0x0828, RW},
	{"IPU_2_DS_2_ROI_EN",           0x082C, RW},
	{"IPU_2_DS_2_ROI_SIZE",         0x0830, RW},
	{"IPU_2_DS_3_ROI_EN",           0x0834, RW},
	{"IPU_2_DS_3_ROI_SIZE",         0x0838, RW},
	{"IPU_2_DS_4_ROI_EN",           0x083C, RW},
	{"IPU_2_DS_4_ROI_SIZE",         0x0840, RW},
	{"IPU_2_US_EN",                 0x0844, RW},
	{"IPU_2_US_STEP",               0x0848, RW},
	{"IPU_2_DS_0_EN",               0x084C, RW},
	{"IPU_2_DS_0_STEP",             0x0850, RW},
	{"IPU_2_DS_1_EN",               0x0854, RW},
	{"IPU_2_DS_1_STEP",             0x0858, RW},
	{"IPU_2_DS_2_EN",               0x085C, RW},
	{"IPU_2_DS_2_STEP",             0x0860, RW},
	{"IPU_2_DS_3_EN",               0x0864, RW},
	{"IPU_2_DS_3_STEP",             0x0868, RW},
	{"IPU_2_DS_4_EN",               0x086C, RW},
	{"IPU_2_DS_4_STEP",             0x0870, RW},
	{"IPU_2_OSD_EN",                0x0874, RW},
	{"IPU_2_OSD_0_ROI_0_START",     0x0878, RW},
	{"IPU_2_OSD_0_ROI_0_SIZE",      0x087C, RW},
	{"IPU_2_OSD_0_ROI_1_START",     0x0880, RW},
	{"IPU_2_OSD_0_ROI_1_SIZE",      0x0884, RW},
	{"IPU_2_OSD_0_ROI_2_START",     0x0888, RW},
	{"IPU_2_OSD_0_ROI_2_SIZE",      0x088C, RW},
	{"IPU_2_OSD_1_ROI_0_START",     0x0890, RW},
	{"IPU_2_OSD_1_ROI_0_SIZE",      0x0894, RW},
	{"IPU_2_OSD_1_ROI_1_START",     0x0898, RW},
	{"IPU_2_OSD_1_ROI_1_SIZE",      0x089C, RW},
	{"IPU_2_OSD_1_ROI_2_START",     0x08A0, RW},
	{"IPU_2_OSD_1_ROI_2_SIZE",      0x08A4, RW},
	{"IPU_2_OSD_2_ROI_0_START",     0x08A8, RW},
	{"IPU_2_OSD_2_ROI_0_SIZE",      0x08AC, RW},
	{"IPU_2_OSD_2_ROI_1_START",     0x08B0, RW},
	{"IPU_2_OSD_2_ROI_1_SIZE",      0x08B4, RW},
	{"IPU_2_OSD_2_ROI_2_START",     0x08B8, RW},
	{"IPU_2_OSD_2_ROI_2_SIZE",      0x08BC, RW},
	{"IPU_2_OSD_STA_ENABLE",        0x08C0, RW},
	{"IPU_2_OSD_0_STA_ROI_0_START", 0x08C4, RW},
	{"IPU_2_OSD_0_STA_ROI_0_SIZE",  0x08C8, RW},
	{"IPU_2_OSD_0_STA_ROI_1_START", 0x08CC, RW},
	{"IPU_2_OSD_0_STA_ROI_1_SIZE",  0x08D0, RW},
	{"IPU_2_OSD_0_STA_ROI_2_START", 0x08D4, RW},
	{"IPU_2_OSD_0_STA_ROI_2_SIZE",  0x08D8, RW},
	{"IPU_2_OSD_0_STA_ROI_3_START", 0x08DC, RW},
	{"IPU_2_OSD_0_STA_ROI_3_SIZE",  0x08E0, RW},
	{"IPU_2_OSD_0_STA_ROI_4_START", 0x08E4, RW},
	{"IPU_2_OSD_0_STA_ROI_4_SIZE",  0x08E8, RW},
	{"IPU_2_OSD_0_STA_ROI_5_START", 0x08EC, RW},
	{"IPU_2_OSD_0_STA_ROI_5_SIZE",  0x08F0, RW},
	{"IPU_2_OSD_0_STA_ROI_6_START", 0x08F4, RW},
	{"IPU_2_OSD_0_STA_ROI_6_SIZE",  0x08F8, RW},
	{"IPU_2_OSD_0_STA_ROI_7_START", 0x08FC, RW},
	{"IPU_2_OSD_0_STA_ROI_7_SIZE",  0x0900, RW},
	{"IPU_2_OSD_1_STA_ROI_0_START", 0x0904, RW},
	{"IPU_2_OSD_1_STA_ROI_0_SIZE",  0x0908, RW},
	{"IPU_2_OSD_1_STA_ROI_1_START", 0x090C, RW},
	{"IPU_2_OSD_1_STA_ROI_1_SIZE",  0x0910, RW},
	{"IPU_2_OSD_1_STA_ROI_2_START", 0x0914, RW},
	{"IPU_2_OSD_1_STA_ROI_2_SIZE",  0x0918, RW},
	{"IPU_2_OSD_1_STA_ROI_3_START", 0x091C, RW},
	{"IPU_2_OSD_1_STA_ROI_3_SIZE",  0x0920, RW},
	{"IPU_2_OSD_1_STA_ROI_4_START", 0x0924, RW},
	{"IPU_2_OSD_1_STA_ROI_4_SIZE",  0x0928, RW},
	{"IPU_2_OSD_1_STA_ROI_5_START", 0x092C, RW},
	{"IPU_2_OSD_1_STA_ROI_5_SIZE",  0x0930, RW},
	{"IPU_2_OSD_1_STA_ROI_6_START", 0x0934, RW},
	{"IPU_2_OSD_1_STA_ROI_6_SIZE",  0x0938, RW},
	{"IPU_2_OSD_1_STA_ROI_7_START", 0x093C, RW},
	{"IPU_2_OSD_1_STA_ROI_7_SIZE",  0x0940, RW},
	{"IPU_2_OSD_2_STA_ROI_0_START", 0x0944, RW},
	{"IPU_2_OSD_2_STA_ROI_0_SIZE",  0x0948, RW},
	{"IPU_2_OSD_2_STA_ROI_1_START", 0x094C, RW},
	{"IPU_2_OSD_2_STA_ROI_1_SIZE",  0x0950, RW},
	{"IPU_2_OSD_2_STA_ROI_2_START", 0x0954, RW},
	{"IPU_2_OSD_2_STA_ROI_2_SIZE",  0x0958, RW},
	{"IPU_2_OSD_2_STA_ROI_3_START", 0x095C, RW},
	{"IPU_2_OSD_2_STA_ROI_3_SIZE",  0x0960, RW},
	{"IPU_2_OSD_2_STA_ROI_4_START", 0x0964, RW},
	{"IPU_2_OSD_2_STA_ROI_4_SIZE",  0x0968, RW},
	{"IPU_2_OSD_2_STA_ROI_5_START", 0x096C, RW},
	{"IPU_2_OSD_2_STA_ROI_5_SIZE",  0x0970, RW},
	{"IPU_2_OSD_2_STA_ROI_6_START", 0x0974, RW},
	{"IPU_2_OSD_2_STA_ROI_6_SIZE",  0x0978, RW},
	{"IPU_2_OSD_2_STA_ROI_7_START", 0x097C, RW},
	{"IPU_2_OSD_2_STA_ROI_7_SIZE",  0x0980, RW},
	{"IPU_2_OSD_STA_LEVEL",         0x0984, RW},
	{"IPU_2_OSD_0_ROI_0_ADDR",      0x0988, RW},
	{"IPU_2_OSD_0_ROI_1_ADDR",      0x098C, RW},
	{"IPU_2_OSD_0_ROI_2_ADDR",      0x0990, RW},
	{"IPU_2_OSD_1_ROI_0_ADDR",      0x0994, RW},
	{"IPU_2_OSD_1_ROI_1_ADDR",      0x0998, RW},
	{"IPU_2_OSD_1_ROI_2_ADDR",      0x099C, RW},
	{"IPU_2_OSD_2_ROI_0_ADDR",      0x09A0, RW},
	{"IPU_2_OSD_2_ROI_1_ADDR",      0x09A4, RW},
	{"IPU_2_OSD_2_ROI_2_ADDR",      0x09A8, RW},
	{"IPU_2_US_DDR_STRIDE_LEN_Y",   0x09B8, RW},
	{"IPU_2_US_DDR_STRIDE_LEN_UV",  0x09BC, RW},
	{"IPU_2_DS_0_DDR_STRIDE_LEN_Y", 0x09C0, RW},
	{"IPU_2_DS_0_DDR_STRIDE_LEN_UV",0x09C4, RW},
	{"IPU_2_DS_1_DDR_STRIDE_LEN_Y", 0x09C8, RW},
	{"IPU_2_DS_1_DDR_STRIDE_LEN_UV",0x09CC, RW},
	{"IPU_2_DS_2_DDR_STRIDE_LEN_Y", 0x09D0, RW},
	{"IPU_2_DS_2_DDR_STRIDE_LEN_UV",0x09D4, RW},
	{"IPU_2_DS_3_DDR_STRIDE_LEN_Y", 0x09D8, RW},
	{"IPU_2_DS_3_DDR_STRIDE_LEN_UV",0x09DC, RW},
	{"IPU_2_DS_4_DDR_STRIDE_LEN_Y", 0x09E0, RW},
	{"IPU_2_DS_4_DDR_STRIDE_LEN_UV",0x09E4, RW},
	/*0xC04*/
	{"IPU_3_SRC_WIDTH",             0x0C04, RW},
	{"IPU_3_SRC_HEIGHT",            0x0C08, RW},
	{"IPU_3_RD_DDR_STRIDE_LEN_Y",   0x0C0C, RW},
	{"IPU_3_RD_DDR_STRIDE_LEN_UV",  0x0C10, RW},
	{"IPU_3_US_ROI_EN",             0x0C14, RW},
	{"IPU_3_US_ROI_SIZE",           0x0C18, RW},
	{"IPU_3_DS_0_ROI_EN",           0x0C1C, RW},
	{"IPU_3_DS_0_ROI_SIZE",         0x0C20, RW},
	{"IPU_3_DS_1_ROI_EN",           0x0C24, RW},
	{"IPU_3_DS_1_ROI_SIZE",         0x0C28, RW},
	{"IPU_3_DS_2_ROI_EN",           0x0C2C, RW},
	{"IPU_3_DS_2_ROI_SIZE",         0x0C30, RW},
	{"IPU_3_DS_3_ROI_EN",           0x0C34, RW},
	{"IPU_3_DS_3_ROI_SIZE",         0x0C38, RW},
	{"IPU_3_DS_4_ROI_EN",           0x0C3C, RW},
	{"IPU_3_DS_4_ROI_SIZE",         0x0C40, RW},
	{"IPU_3_US_EN",                 0x0C44, RW},
	{"IPU_3_US_STEP",               0x0C48, RW},
	{"IPU_3_DS_0_EN",               0x0C4C, RW},
	{"IPU_3_DS_0_STEP",             0x0C50, RW},
	{"IPU_3_DS_1_EN",               0x0C54, RW},
	{"IPU_3_DS_1_STEP",             0x0C58, RW},
	{"IPU_3_DS_2_EN",               0x0C5C, RW},
	{"IPU_3_DS_2_STEP",             0x0C60, RW},
	{"IPU_3_DS_3_EN",               0x0C64, RW},
	{"IPU_3_DS_3_STEP",             0x0C68, RW},
	{"IPU_3_DS_4_EN",               0x0C6C, RW},
	{"IPU_3_DS_4_STEP",             0x0C70, RW},
	{"IPU_3_OSD_EN",                0x0C74, RW},
	{"IPU_3_OSD_0_ROI_0_START",     0x0C78, RW},
	{"IPU_3_OSD_0_ROI_0_SIZE",      0x0C7C, RW},
	{"IPU_3_OSD_0_ROI_1_START",     0x0C80, RW},
	{"IPU_3_OSD_0_ROI_1_SIZE",      0x0C84, RW},
	{"IPU_3_OSD_0_ROI_2_START",     0x0C88, RW},
	{"IPU_3_OSD_0_ROI_2_SIZE",      0x0C8C, RW},
	{"IPU_3_OSD_1_ROI_0_START",     0x0C90, RW},
	{"IPU_3_OSD_1_ROI_0_SIZE",      0x0C94, RW},
	{"IPU_3_OSD_1_ROI_1_START",     0x0C98, RW},
	{"IPU_3_OSD_1_ROI_1_SIZE",      0x0C9C, RW},
	{"IPU_3_OSD_1_ROI_2_START",     0x0CA0, RW},
	{"IPU_3_OSD_1_ROI_2_SIZE",      0x0CA4, RW},
	{"IPU_3_OSD_2_ROI_0_START",     0x0CA8, RW},
	{"IPU_3_OSD_2_ROI_0_SIZE",      0x0CAC, RW},
	{"IPU_3_OSD_2_ROI_1_START",     0x0CB0, RW},
	{"IPU_3_OSD_2_ROI_1_SIZE",      0x0CB4, RW},
	{"IPU_3_OSD_2_ROI_2_START",     0x0CB8, RW},
	{"IPU_3_OSD_2_ROI_2_SIZE",      0x0CBC, RW},
	{"IPU_3_OSD_STA_ENABLE",        0x0CC0, RW},
	{"IPU_3_OSD_0_STA_ROI_0_START", 0x0CC4, RW},
	{"IPU_3_OSD_0_STA_ROI_0_SIZE",  0x0CC8, RW},
	{"IPU_3_OSD_0_STA_ROI_1_START", 0x0CCC, RW},
	{"IPU_3_OSD_0_STA_ROI_1_SIZE",  0x0CD0, RW},
	{"IPU_3_OSD_0_STA_ROI_2_START", 0x0CD4, RW},
	{"IPU_3_OSD_0_STA_ROI_2_SIZE",  0x0CD8, RW},
	{"IPU_3_OSD_0_STA_ROI_3_START", 0x0CDC, RW},
	{"IPU_3_OSD_0_STA_ROI_3_SIZE",  0x0CE0, RW},
	{"IPU_3_OSD_0_STA_ROI_4_START", 0x0CE4, RW},
	{"IPU_3_OSD_0_STA_ROI_4_SIZE",  0x0CE8, RW},
	{"IPU_3_OSD_0_STA_ROI_5_START", 0x0CEC, RW},
	{"IPU_3_OSD_0_STA_ROI_5_SIZE",  0x0CF0, RW},
	{"IPU_3_OSD_0_STA_ROI_6_START", 0x0CF4, RW},
	{"IPU_3_OSD_0_STA_ROI_6_SIZE",  0x0CF8, RW},
	{"IPU_3_OSD_0_STA_ROI_7_START", 0x0CFC, RW},
	{"IPU_3_OSD_0_STA_ROI_7_SIZE",  0x0D00, RW},
	{"IPU_3_OSD_1_STA_ROI_0_START", 0x0D04, RW},
	{"IPU_3_OSD_1_STA_ROI_0_SIZE",  0x0D08, RW},
	{"IPU_3_OSD_1_STA_ROI_1_START", 0x0D0C, RW},
	{"IPU_3_OSD_1_STA_ROI_1_SIZE",  0x0D10, RW},
	{"IPU_3_OSD_1_STA_ROI_2_START", 0x0D14, RW},
	{"IPU_3_OSD_1_STA_ROI_2_SIZE",  0x0D18, RW},
	{"IPU_3_OSD_1_STA_ROI_3_START", 0x0D1C, RW},
	{"IPU_3_OSD_1_STA_ROI_3_SIZE",  0x0D20, RW},
	{"IPU_3_OSD_1_STA_ROI_4_START", 0x0D24, RW},
	{"IPU_3_OSD_1_STA_ROI_4_SIZE",  0x0D28, RW},
	{"IPU_3_OSD_1_STA_ROI_5_START", 0x0D2C, RW},
	{"IPU_3_OSD_1_STA_ROI_5_SIZE",  0x0D30, RW},
	{"IPU_3_OSD_1_STA_ROI_6_START", 0x0D34, RW},
	{"IPU_3_OSD_1_STA_ROI_6_SIZE",  0x0D38, RW},
	{"IPU_3_OSD_1_STA_ROI_7_START", 0x0D3C, RW},
	{"IPU_3_OSD_1_STA_ROI_7_SIZE",  0x0D40, RW},
	{"IPU_3_OSD_2_STA_ROI_0_START", 0x0D44, RW},
	{"IPU_3_OSD_2_STA_ROI_0_SIZE",  0x0D48, RW},
	{"IPU_3_OSD_2_STA_ROI_1_START", 0x0D4C, RW},
	{"IPU_3_OSD_2_STA_ROI_1_SIZE",  0x0D50, RW},
	{"IPU_3_OSD_2_STA_ROI_2_START", 0x0D54, RW},
	{"IPU_3_OSD_2_STA_ROI_2_SIZE",  0x0D58, RW},
	{"IPU_3_OSD_2_STA_ROI_3_START", 0x0D5C, RW},
	{"IPU_3_OSD_2_STA_ROI_3_SIZE",  0x0D60, RW},
	{"IPU_3_OSD_2_STA_ROI_4_START", 0x0D64, RW},
	{"IPU_3_OSD_2_STA_ROI_4_SIZE",  0x0D68, RW},
	{"IPU_3_OSD_2_STA_ROI_5_START", 0x0D6C, RW},
	{"IPU_3_OSD_2_STA_ROI_5_SIZE",  0x0D70, RW},
	{"IPU_3_OSD_2_STA_ROI_6_START", 0x0D74, RW},
	{"IPU_3_OSD_2_STA_ROI_6_SIZE",  0x0D78, RW},
	{"IPU_3_OSD_2_STA_ROI_7_START", 0x0D7C, RW},
	{"IPU_3_OSD_2_STA_ROI_7_SIZE",  0x0D80, RW},
	{"IPU_3_OSD_STA_LEVEL",         0x0D84, RW},
	{"IPU_3_OSD_0_ROI_0_ADDR",      0x0D88, RW},
	{"IPU_3_OSD_0_ROI_1_ADDR",      0x0D8C, RW},
	{"IPU_3_OSD_0_ROI_2_ADDR",      0x0D90, RW},
	{"IPU_3_OSD_1_ROI_0_ADDR",      0x0D94, RW},
	{"IPU_3_OSD_1_ROI_1_ADDR",      0x0D98, RW},
	{"IPU_3_OSD_1_ROI_2_ADDR",      0x0D9C, RW},
	{"IPU_3_OSD_2_ROI_0_ADDR",      0x0DA0, RW},
	{"IPU_3_OSD_2_ROI_1_ADDR",      0x0DA4, RW},
	{"IPU_3_OSD_2_ROI_2_ADDR",      0x0DA8, RW},
	{"IPU_3_US_DDR_STRIDE_LEN_Y",   0x0DB8, RW},
	{"IPU_3_US_DDR_STRIDE_LEN_UV",  0x0DBC, RW},
	{"IPU_3_DS_0_DDR_STRIDE_LEN_Y", 0x0DC0, RW},
	{"IPU_3_DS_0_DDR_STRIDE_LEN_UV",0x0DC4, RW},
	{"IPU_3_DS_1_DDR_STRIDE_LEN_Y", 0x0DC8, RW},
	{"IPU_3_DS_1_DDR_STRIDE_LEN_UV",0x0DCC, RW},
	{"IPU_3_DS_2_DDR_STRIDE_LEN_Y", 0x0DD0, RW},
	{"IPU_3_DS_2_DDR_STRIDE_LEN_UV",0x0DD4, RW},
	{"IPU_3_DS_3_DDR_STRIDE_LEN_Y", 0x0DD8, RW},
	{"IPU_3_DS_3_DDR_STRIDE_LEN_UV",0x0DDC, RW},
	{"IPU_3_DS_4_DDR_STRIDE_LEN_Y", 0x0DE0, RW},
	{"IPU_3_DS_4_DDR_STRIDE_LEN_UV",0x0DE4, RW},
	/*0xE50*/ 
	{"IPU_INT_MASK",                0x0E50, RW},
	{"IPU_INT_STATUS",              0x0E54, W1C},
	{"IPU_CFG_RDY",                 0x0E58, RW},
	{"IPU_CFG_SEL",                 0x0E5C, RW},
	{"IPU_BUS_CFG",                 0x0E60, RW},
	{"IPU_BUS_CTRL_WM_0",           0x0E64, RW},
	{"IPU_BUS_CTRL_WM_1",           0x0E68, RW},
	{"IPU_BUS_CTRL_WM_2",           0x0E6C, RW},
	{"IPU_BUS_CTRL_WM_3",           0x0E70, RW},
	{"IPU_BUS_CTRL_WM_4",           0x0E74, RW},
	{"IPU_BUS_CTRL_WM_5",           0x0E78, RW},
	{"IPU_BUS_CTRL_WM_6",           0x0E7C, RW},
	{"IPU_BUS_CTRL_WM_7",           0x0E80, RW},
	{"IPU_BUS_CTRL_WM_8",           0x0E84, RW},
	{"IPU_BUS_CTRL_WM_9",           0x0E88, RW},
	{"IPU_BUS_CTRL_WM_10",          0x0E8C, RW},
	{"IPU_BUS_CTRL_WM_11",          0x0E90, RW},
	{"IPU_BUS_CTRL_WM_12",          0x0E94, RW},
	{"IPU_BUS_CTRL_RM_0",           0x0E98, RW},
	{"IPU_BUS_CTRL_RM_1",           0x0E9C, RW},
	{"IPU_BUS_CTRL_RM_2",           0x0EA0, RW},
	{"IPU_BUS_CTRL_RM_3",           0x0EA4, RW},
	{"IPU_BUS_CTRL_RM_4",           0x0EA8, RW},
	{"IPU_FRAME_ID",                0x0EAC, RO},
	{"IPU_OSD_COLOR_0",             0x0EB0, RW},
	{"IPU_OSD_COLOR_1",             0x0EB4, RW},
	{"IPU_OSD_COLOR_2",             0x0EB8, RW},
	{"IPU_OSD_COLOR_3",             0x0EBC, RW},
	{"IPU_OSD_COLOR_4",             0x0EC0, RW},
	{"IPU_OSD_COLOR_5",             0x0EC4, RW},
	{"IPU_OSD_COLOR_6",             0x0EC8, RW},
	{"IPU_OSD_COLOR_7",             0x0ECC, RW},
	{"IPU_OSD_COLOR_8",             0x0ED0, RW},
	{"IPU_OSD_COLOR_9",             0x0ED4, RW},
	{"IPU_OSD_COLOR_10",            0x0ED8, RW},
	{"IPU_OSD_COLOR_11",            0x0EDC, RW},
	{"IPU_OSD_COLOR_12",            0x0EE0, RW},
	{"IPU_OSD_COLOR_13",            0x0EE4, RW},
	{"IPU_OSD_COLOR_14",            0x0EE8, RW},
	{"IPU_CFG",                     0x0EEC, RW},
	{"IPU_RD_DDR_ADDR_Y",           0x0EF0, RW},
	{"IPU_RD_DDR_ADDR_UV",          0x0EF4, RW},
	{"IPU_US_DDR_Y",                0x0EF8, RW},
	{"IPU_US_DDR_UV",               0x0EFC, RW},
	{"IPU_DS_0_DDR_Y",              0x0F00, RW},
	{"IPU_DS_0_DDR_UV",             0x0F04, RW},
	{"IPU_DS_1_DDR_Y",              0x0F08, RW},
	{"IPU_DS_1_DDR_UV",             0x0F0C, RW},
	{"IPU_DS_2_DDR_Y",              0x0F10, RW},
	{"IPU_DS_2_DDR_UV",             0x0F14, RW},
	{"IPU_DS_3_DDR_Y",              0x0F18, RW},
	{"IPU_DS_3_DDR_UV",             0x0F1C, RW},
	{"IPU_DS_4_DDR_Y",              0x0F20, RW},
	{"IPU_DS_4_DDR_UV",             0x0F24, RW},
	{"IPU_OSD_0_STA_0_BIN01",       0x0F28, RO},
	{"IPU_OSD_0_STA_0_BIN23",       0x0F2C, RO},
	{"IPU_OSD_0_STA_1_BIN01",       0x0F30, RO},
	{"IPU_OSD_0_STA_1_BIN23",       0x0F34, RO},
	{"IPU_OSD_0_STA_2_BIN01",       0x0F38, RO},
	{"IPU_OSD_0_STA_2_BIN23",       0x0F3C, RO},
	{"IPU_OSD_0_STA_3_BIN01",       0x0F40, RO},
	{"IPU_OSD_0_STA_3_BIN23",       0x0F44, RO},
	{"IPU_OSD_0_STA_4_BIN01",       0x0F48, RO},
	{"IPU_OSD_0_STA_4_BIN23",       0x0F4C, RO},
	{"IPU_OSD_0_STA_5_BIN01",       0x0F50, RO},
	{"IPU_OSD_0_STA_5_BIN23",       0x0F54, RO},
	{"IPU_OSD_0_STA_6_BIN01",       0x0F58, RO},
	{"IPU_OSD_0_STA_6_BIN23",       0x0F5C, RO},
	{"IPU_OSD_0_STA_7_BIN01",       0x0F60, RO},
	{"IPU_OSD_0_STA_7_BIN23",       0x0F64, RO},
	{"IPU_OSD_1_STA_0_BIN01",       0x0F68, RO},
	{"IPU_OSD_1_STA_0_BIN23",       0x0F6C, RO},
	{"IPU_OSD_1_STA_1_BIN01",       0x0F70, RO},
	{"IPU_OSD_1_STA_1_BIN23",       0x0F74, RO},
	{"IPU_OSD_1_STA_2_BIN01",       0x0F78, RO},
	{"IPU_OSD_1_STA_2_BIN23",       0x0F7C, RO},
	{"IPU_OSD_1_STA_3_BIN01",       0x0F80, RO},
	{"IPU_OSD_1_STA_3_BIN23",       0x0F84, RO},
	{"IPU_OSD_1_STA_4_BIN01",       0x0F88, RO},
	{"IPU_OSD_1_STA_4_BIN23",       0x0F8C, RO},
	{"IPU_OSD_1_STA_5_BIN01",       0x0F90, RO},
	{"IPU_OSD_1_STA_5_BIN23",       0x0F94, RO},
	{"IPU_OSD_1_STA_6_BIN01",       0x0F98, RO},
	{"IPU_OSD_1_STA_6_BIN23",       0x0F9C, RO},
	{"IPU_OSD_1_STA_7_BIN01",       0x0FA0, RO},
	{"IPU_OSD_1_STA_7_BIN23",       0x0FA4, RO},
	{"IPU_OSD_2_STA_0_BIN01",       0x0FA8, RO},
	{"IPU_OSD_2_STA_0_BIN23",       0x0FAC, RO},
	{"IPU_OSD_2_STA_1_BIN01",       0x0FB0, RO},
	{"IPU_OSD_2_STA_1_BIN23",       0x0FB4, RO},
	{"IPU_OSD_2_STA_2_BIN01",       0x0FB8, RO},
	{"IPU_OSD_2_STA_2_BIN23",       0x0FBC, RO},
	{"IPU_OSD_2_STA_3_BIN01",       0x0FC0, RO},
	{"IPU_OSD_2_STA_3_BIN23",       0x0FC4, RO},
	{"IPU_OSD_2_STA_4_BIN01",       0x0FC8, RO},
	{"IPU_OSD_2_STA_4_BIN23",       0x0FCC, RO},
	{"IPU_OSD_2_STA_5_BIN01",       0x0FD0, RO},
	{"IPU_OSD_2_STA_5_BIN23",       0x0FD4, RO},
	{"IPU_OSD_2_STA_6_BIN01",       0x0FD8, RO},
	{"IPU_OSD_2_STA_6_BIN23",       0x0FDC, RO},
	{"IPU_OSD_2_STA_7_BIN01",       0x0FE0, RO},
	{"IPU_OSD_2_STA_7_BIN23",       0x0FE4, RO},
	{"IPU_DDR_START",               0x0FE8, WO},
	{"IPU_TEST_Y_SET",              0x0FEC, RW},
	{"IPU_TEST_U_SET",              0x0FF0, RW},
	{"IPU_TEST_V_SET",              0x0FF4, RW},
	{"IPU_PRE_INT_SET",             0x0FF8, RW},
};

enum ipu_reg_field{
	IPU_F_SRC_WIDTH,
	IPU_F_SRC_HEIGHT,
	IPU_F_RD_DDR_STRIDE_LEN_Y,
	IPU_F_RD_DDR_STRIDE_LEN_UV,
	IPU_F_US_ROI_START_Y,
	IPU_F_US_ROI_START_X,
	IPU_F_US_ROI_EN,
	IPU_F_US_ROI_HEIGHT,
	IPU_F_US_ROI_WIDTH,
	IPU_F_DS_0_ROI_START_Y,
	IPU_F_DS_0_ROI_START_X,
	IPU_F_DS_0_ROI_EN,
	IPU_F_DS_0_ROI_HEIGHT,
	IPU_F_DS_0_ROI_WIDTH,
	IPU_F_DS_1_ROI_START_Y,
	IPU_F_DS_1_ROI_START_X,
	IPU_F_DS_1_ROI_EN,
	IPU_F_DS_1_ROI_HEIGHT,
	IPU_F_DS_1_ROI_WIDTH,
	IPU_F_DS_2_ROI_START_Y,
	IPU_F_DS_2_ROI_START_X,
	IPU_F_DS_2_ROI_EN,
	IPU_F_DS_2_ROI_HEIGHT,
	IPU_F_DS_2_ROI_WIDTH,
	IPU_F_DS_3_ROI_START_Y,
	IPU_F_DS_3_ROI_START_X,
	IPU_F_DS_3_ROI_EN,
	IPU_F_DS_3_ROI_HEIGHT,
	IPU_F_DS_3_ROI_WIDTH,
	IPU_F_DS_4_ROI_START_Y,
	IPU_F_DS_4_ROI_START_X,
	IPU_F_DS_4_ROI_EN,
	IPU_F_DS_4_ROI_HEIGHT,
	IPU_F_DS_4_ROI_WIDTH,
	IPU_F_US_TGT_HEIGHT,
	IPU_F_US_TGT_WIDTH,
	IPU_F_US_EN,
	IPU_F_US_STEP_Y,
	IPU_F_US_STEP_X,
	IPU_F_DS_0_TGT_HEIGHT,
	IPU_F_DS_0_TGT_WIDTH,
	IPU_F_DS_0_EN,
	IPU_F_DS_0_PRE_Y,
	IPU_F_DS_0_PRE_X,
	IPU_F_DS_0_STEP_Y,
	IPU_F_DS_0_STEP_X,
	IPU_F_DS_1_TGT_HEIGHT,
	IPU_F_DS_1_TGT_WIDTH,
	IPU_F_DS_1_EN,
	IPU_F_DS_1_PRE_Y,
	IPU_F_DS_1_PRE_X,
	IPU_F_DS_1_STEP_Y,
	IPU_F_DS_1_STEP_X,
	IPU_F_DS_2_TGT_HEIGHT,
	IPU_F_DS_2_TGT_WIDTH,
	IPU_F_DS_2_EN,
	IPU_F_DS_2_PRE_Y,
	IPU_F_DS_2_PRE_X,
	IPU_F_DS_2_STEP_Y,
	IPU_F_DS_2_STEP_X,
	IPU_F_DS_3_TGT_HEIGHT,
	IPU_F_DS_3_TGT_WIDTH,
	IPU_F_DS_3_EN,
	IPU_F_DS_3_PRE_Y,
	IPU_F_DS_3_PRE_X,
	IPU_F_DS_3_STEP_Y,
	IPU_F_DS_3_STEP_X,
	IPU_F_DS_4_TGT_HEIGHT,
	IPU_F_DS_4_TGT_WIDTH,
	IPU_F_DS_4_EN,
	IPU_F_DS_4_PRE_Y,
	IPU_F_DS_4_PRE_X,
	IPU_F_DS_4_STEP_Y,
	IPU_F_DS_4_STEP_X,
	IPU_F_DS_2_DDR_ENABLE,
	IPU_F_OSD_2_OVERLAY_MODE,
	IPU_F_OSD_1_OVERLAY_MODE,
	IPU_F_OSD_0_OVERLAY_MODE,
	IPU_F_OSD_2_EN,
	IPU_F_OSD_1_EN,
	IPU_F_OSD_0_EN,
	IPU_F_OSD_0_ROI_0_START_Y,
	IPU_F_OSD_0_ROI_0_START_X,
	IPU_F_OSD_0_ROI_0_HEIGHT,
	IPU_F_OSD_0_ROI_0_WIDTH,
	IPU_F_OSD_0_ROI_1_START_Y,
	IPU_F_OSD_0_ROI_1_START_X,
	IPU_F_OSD_0_ROI_1_HEIGHT,
	IPU_F_OSD_0_ROI_1_WIDTH,
	IPU_F_OSD_0_ROI_2_START_Y,
	IPU_F_OSD_0_ROI_2_START_X,
	IPU_F_OSD_0_ROI_2_HEIGHT,
	IPU_F_OSD_0_ROI_2_WIDTH,
	IPU_F_OSD_1_ROI_0_START_Y,
	IPU_F_OSD_1_ROI_0_START_X,
	IPU_F_OSD_1_ROI_0_HEIGHT,
	IPU_F_OSD_1_ROI_0_WIDTH,
	IPU_F_OSD_1_ROI_1_START_Y,
	IPU_F_OSD_1_ROI_1_START_X,
	IPU_F_OSD_1_ROI_1_HEIGHT,
	IPU_F_OSD_1_ROI_1_WIDTH,
	IPU_F_OSD_1_ROI_2_START_Y,
	IPU_F_OSD_1_ROI_2_START_X,
	IPU_F_OSD_1_ROI_2_HEIGHT,
	IPU_F_OSD_1_ROI_2_WIDTH,
	IPU_F_OSD_2_ROI_0_START_Y,
	IPU_F_OSD_2_ROI_0_START_X,
	IPU_F_OSD_2_ROI_0_HEIGHT,
	IPU_F_OSD_2_ROI_0_WIDTH,
	IPU_F_OSD_2_ROI_1_START_Y,
	IPU_F_OSD_2_ROI_1_START_X,
	IPU_F_OSD_2_ROI_1_HEIGHT,
	IPU_F_OSD_2_ROI_1_WIDTH,
	IPU_F_OSD_2_ROI_2_START_Y,
	IPU_F_OSD_2_ROI_2_START_X,
	IPU_F_OSD_2_ROI_2_HEIGHT,
	IPU_F_OSD_2_ROI_2_WIDTH,
	IPU_F_OSD_2_STA_ENABLE,
	IPU_F_OSD_1_STA_ENABLE,
	IPU_F_OSD_0_STA_ENABLE,
	IPU_F_OSD_0_STA_ROI_0_START_Y,
	IPU_F_OSD_0_STA_ROI_0_START_X,
	IPU_F_OSD_0_STA_ROI_0_HEIGHT,
	IPU_F_OSD_0_STA_ROI_0_WIDTH,
	IPU_F_OSD_0_STA_ROI_1_START_Y,
	IPU_F_OSD_0_STA_ROI_1_START_X,
	IPU_F_OSD_0_STA_ROI_1_HEIGHT,
	IPU_F_OSD_0_STA_ROI_1_WIDTH,
	IPU_F_OSD_0_STA_ROI_2_START_Y,
	IPU_F_OSD_0_STA_ROI_2_START_X,
	IPU_F_OSD_0_STA_ROI_2_HEIGHT,
	IPU_F_OSD_0_STA_ROI_2_WIDTH,
	IPU_F_OSD_0_STA_ROI_3_START_Y,
	IPU_F_OSD_0_STA_ROI_3_START_X,
	IPU_F_OSD_0_STA_ROI_3_HEIGHT,
	IPU_F_OSD_0_STA_ROI_3_WIDTH,
	IPU_F_OSD_0_STA_ROI_4_START_Y,
	IPU_F_OSD_0_STA_ROI_4_START_X,
	IPU_F_OSD_0_STA_ROI_4_HEIGHT,
	IPU_F_OSD_0_STA_ROI_4_WIDTH,
	IPU_F_OSD_0_STA_ROI_5_START_Y,
	IPU_F_OSD_0_STA_ROI_5_START_X,
	IPU_F_OSD_0_STA_ROI_5_HEIGHT,
	IPU_F_OSD_0_STA_ROI_5_WIDTH,
	IPU_F_OSD_0_STA_ROI_6_START_Y,
	IPU_F_OSD_0_STA_ROI_6_START_X,
	IPU_F_OSD_0_STA_ROI_6_HEIGHT,
	IPU_F_OSD_0_STA_ROI_6_WIDTH,
	IPU_F_OSD_0_STA_ROI_7_START_Y,
	IPU_F_OSD_0_STA_ROI_7_START_X,
	IPU_F_OSD_0_STA_ROI_7_HEIGHT,
	IPU_F_OSD_0_STA_ROI_7_WIDTH,
	IPU_F_OSD_1_STA_ROI_0_START_Y,
	IPU_F_OSD_1_STA_ROI_0_START_X,
	IPU_F_OSD_1_STA_ROI_0_HEIGHT,
	IPU_F_OSD_1_STA_ROI_0_WIDTH,
	IPU_F_OSD_1_STA_ROI_1_START_Y,
	IPU_F_OSD_1_STA_ROI_1_START_X,
	IPU_F_OSD_1_STA_ROI_1_HEIGHT,
	IPU_F_OSD_1_STA_ROI_1_WIDTH,
	IPU_F_OSD_1_STA_ROI_2_START_Y,
	IPU_F_OSD_1_STA_ROI_2_START_X,
	IPU_F_OSD_1_STA_ROI_2_HEIGHT,
	IPU_F_OSD_1_STA_ROI_2_WIDTH,
	IPU_F_OSD_1_STA_ROI_3_START_Y,
	IPU_F_OSD_1_STA_ROI_3_START_X,
	IPU_F_OSD_1_STA_ROI_3_HEIGHT,
	IPU_F_OSD_1_STA_ROI_3_WIDTH,
	IPU_F_OSD_1_STA_ROI_4_START_Y,
	IPU_F_OSD_1_STA_ROI_4_START_X,
	IPU_F_OSD_1_STA_ROI_4_HEIGHT,
	IPU_F_OSD_1_STA_ROI_4_WIDTH,
	IPU_F_OSD_1_STA_ROI_5_START_Y,
	IPU_F_OSD_1_STA_ROI_5_START_X,
	IPU_F_OSD_1_STA_ROI_5_HEIGHT,
	IPU_F_OSD_1_STA_ROI_5_WIDTH,
	IPU_F_OSD_1_STA_ROI_6_START_Y,
	IPU_F_OSD_1_STA_ROI_6_START_X,
	IPU_F_OSD_1_STA_ROI_6_HEIGHT,
	IPU_F_OSD_1_STA_ROI_6_WIDTH,
	IPU_F_OSD_1_STA_ROI_7_START_Y,
	IPU_F_OSD_1_STA_ROI_7_START_X,
	IPU_F_OSD_1_STA_ROI_7_HEIGHT,
	IPU_F_OSD_1_STA_ROI_7_WIDTH,
	IPU_F_OSD_2_STA_ROI_0_START_Y,
	IPU_F_OSD_2_STA_ROI_0_START_X,
	IPU_F_OSD_2_STA_ROI_0_HEIGHT,
	IPU_F_OSD_2_STA_ROI_0_WIDTH,
	IPU_F_OSD_2_STA_ROI_1_START_Y,
	IPU_F_OSD_2_STA_ROI_1_START_X,
	IPU_F_OSD_2_STA_ROI_1_HEIGHT,
	IPU_F_OSD_2_STA_ROI_1_WIDTH,
	IPU_F_OSD_2_STA_ROI_2_START_Y,
	IPU_F_OSD_2_STA_ROI_2_START_X,
	IPU_F_OSD_2_STA_ROI_2_HEIGHT,
	IPU_F_OSD_2_STA_ROI_2_WIDTH,
	IPU_F_OSD_2_STA_ROI_3_START_Y,
	IPU_F_OSD_2_STA_ROI_3_START_X,
	IPU_F_OSD_2_STA_ROI_3_HEIGHT,
	IPU_F_OSD_2_STA_ROI_3_WIDTH,
	IPU_F_OSD_2_STA_ROI_4_START_Y,
	IPU_F_OSD_2_STA_ROI_4_START_X,
	IPU_F_OSD_2_STA_ROI_4_HEIGHT,
	IPU_F_OSD_2_STA_ROI_4_WIDTH,
	IPU_F_OSD_2_STA_ROI_5_START_Y,
	IPU_F_OSD_2_STA_ROI_5_START_X,
	IPU_F_OSD_2_STA_ROI_5_HEIGHT,
	IPU_F_OSD_2_STA_ROI_5_WIDTH,
	IPU_F_OSD_2_STA_ROI_6_START_Y,
	IPU_F_OSD_2_STA_ROI_6_START_X,
	IPU_F_OSD_2_STA_ROI_6_HEIGHT,
	IPU_F_OSD_2_STA_ROI_6_WIDTH,
	IPU_F_OSD_2_STA_ROI_7_START_Y,
	IPU_F_OSD_2_STA_ROI_7_START_X,
	IPU_F_OSD_2_STA_ROI_7_HEIGHT,
	IPU_F_OSD_2_STA_ROI_7_WIDTH,
	IPU_F_OSD_STA_LEVEL_2,
	IPU_F_OSD_STA_LEVEL_1,
	IPU_F_OSD_STA_LEVEL_0,
	IPU_F_OSD_0_ROI_0_ADDR,
	IPU_F_OSD_0_ROI_1_ADDR,
	IPU_F_OSD_0_ROI_2_ADDR,
	IPU_F_OSD_1_ROI_0_ADDR,
	IPU_F_OSD_1_ROI_1_ADDR,
	IPU_F_OSD_1_ROI_2_ADDR,
	IPU_F_OSD_2_ROI_0_ADDR,
	IPU_F_OSD_2_ROI_1_ADDR,
	IPU_F_OSD_2_ROI_2_ADDR,
	IPU_F_US_DDR_STRIDE_LEN_Y,
	IPU_F_US_DDR_STRIDE_LEN_UV,
	IPU_F_DS_0_DDR_STRIDE_LEN_Y,
	IPU_F_DS_0_DDR_STRIDE_LEN_UV,
	IPU_F_DS_1_DDR_STRIDE_LEN_Y,
	IPU_F_DS_1_DDR_STRIDE_LEN_UV,
	IPU_F_DS_2_DDR_STRIDE_LEN_Y,
	IPU_F_DS_2_DDR_STRIDE_LEN_UV,
	IPU_F_DS_3_DDR_STRIDE_LEN_Y,
	IPU_F_DS_3_DDR_STRIDE_LEN_UV,
	IPU_F_DS_4_DDR_STRIDE_LEN_Y,
	IPU_F_DS_4_DDR_STRIDE_LEN_UV,
	IPU_F_SIZE_ERR_H,
	IPU_F_SIZE_ERR_W,
	IPU_F_CHECKSUM_Y,
	IPU_F_CHECKSUM_UV,
	IPU_F_LAYER_0_US_ACTIVE,
	IPU_F_LAYER_2_DS_ACTIVE,
	IPU_F_LAYER_1_DS_ACTIVE,
	IPU_F_LAYER_0_DS_ACTIVE,
	IPU_F_LAYER_2_STATE,
	IPU_F_LAYER_1_STATE,
	IPU_F_LAYER_0_STATE,
	IPU_F_LAYER_0_RD_CNT,
	IPU_F_LAYER_0_WR_LINE_CNT,
	IPU_F_LAYER_1_RD_CNT,
	IPU_F_LAYER_1_WR_LINE_CNT,
	IPU_F_LAYER_2_RD_CNT,
	IPU_F_LAYER_2_WR_LINE_CNT,
	IPU_F_LAYER_0_REQ_LINE_CNT,
	IPU_F_LAYER_1_REQ_LINE_CNT,
	IPU_F_LAYER_2_REQ_LINE_CNT,
	IPU_F_LINE_DELAY_SET,
	IPU_F_ERR_CLR,
	IPU_F_BUF_ERR,
	IPU_F_STA_SIZE_ERR_H,
	IPU_F_STA_SIZE_ERR_W,
	IPU_F_WD_DDR_FIFO_THRED_5,
	
	IPU_F_PRE_INT_1_ENABLE,
	IPU_F_PRE_INT_0_ENABLE,
	IPU_F_OSD_2_DROP_ENABLE,
	IPU_F_OSD_1_DROP_ENABLE,
	IPU_F_OSD_0_DROP_ENABLE,
	IPU_F_DS_4_DROP_ENABLE,
	IPU_F_DS_3_DROP_ENABLE,
	IPU_F_DS_2_DROP_ENABLE,
	IPU_F_DS_1_DROP_ENABLE,
	IPU_F_DS_0_DROP_ENABLE,
	IPU_F_US_DROP_ENABLE,
	IPU_F_DS_4_DONE_ENABLE,
	IPU_F_DS_3_DONE_ENABLE,
	IPU_F_DS_2_DONE_ENABLE,
	IPU_F_DS_1_DONE_ENABLE,
	IPU_F_DS_0_DONE_ENABLE,
	IPU_F_US_DONE_ENABLE,
	IPU_F_FRAME_DONE_ENABLE,
	IPU_F_FRAME_START_ENABLE,
	IPU_F_PRE_INT_1_DONE,
	IPU_F_PRE_INT_0_DONE,
	IPU_F_OSD_2_DROP,
	IPU_F_OSD_1_DROP,
	IPU_F_OSD_0_DROP,
	IPU_F_DS_4_DROP,
	IPU_F_DS_3_DROP,
	IPU_F_DS_2_DROP,
	IPU_F_DS_1_DROP,
	IPU_F_DS_0_DROP,
	IPU_F_US_DROP,
	IPU_F_DS_4_DONE,
	IPU_F_DS_3_DONE,
	IPU_F_DS_2_DONE,
	IPU_F_DS_1_DONE,
	IPU_F_DS_0_DONE,
	IPU_F_US_DONE,
	IPU_F_FRAME_DONE,
	IPU_F_FRAME_START,
	IPU_F_SHD_RDY_COMMON,
	IPU_F_SHD_RDY_3,
	IPU_F_SHD_RDY_2,
	IPU_F_SHD_RDY_1,
	IPU_F_SHD_RDY_0,
	IPU_F_CFG_SEL,
	IPU_F_AXI_ID,
	IPU_F_WM_MAXLEN_M0,
	IPU_F_WM_ENDIAN_M0,
	IPU_F_WM_PRIORITY_M0,
	IPU_F_WM_MAXLEN_M1,
	IPU_F_WM_ENDIAN_M1,
	IPU_F_WM_PRIORITY_M1,
	IPU_F_WM_MAXLEN_M2,
	IPU_F_WM_ENDIAN_M2,
	IPU_F_WM_PRIORITY_M2,
	IPU_F_WM_MAXLEN_M3,
	IPU_F_WM_ENDIAN_M3,
	IPU_F_WM_PRIORITY_M3,
	IPU_F_WM_MAXLEN_M4,
	IPU_F_WM_ENDIAN_M4,
	IPU_F_WM_PRIORITY_M4,
	IPU_F_WM_MAXLEN_M5,
	IPU_F_WM_ENDIAN_M5,
	IPU_F_WM_PRIORITY_M5,
	IPU_F_WM_MAXLEN_M6,
	IPU_F_WM_ENDIAN_M6,
	IPU_F_WM_PRIORITY_M6,
	IPU_F_WM_MAXLEN_M7,
	IPU_F_WM_ENDIAN_M7,
	IPU_F_WM_PRIORITY_M7,
	IPU_F_WM_MAXLEN_M8,
	IPU_F_WM_ENDIAN_M8,
	IPU_F_WM_PRIORITY_M8,
	IPU_F_WM_MAXLEN_M9,
	IPU_F_WM_ENDIAN_M9,
	IPU_F_WM_PRIORITY_M9,
	IPU_F_WM_MAXLEN_M10,
	IPU_F_WM_ENDIAN_M10,
	IPU_F_WM_PRIORITY_M10,
	IPU_F_WM_MAXLEN_M11,
	IPU_F_WM_ENDIAN_M11,
	IPU_F_WM_PRIORITY_M11,
	IPU_F_WM_MAXLEN_M12,
	IPU_F_WM_ENDIAN_M12,
	IPU_F_WM_PRIORITY_M12,
	IPU_F_RM_MAXLEN_M0,
	IPU_F_RM_ENDIAN_M0,
	IPU_F_RM_PRIORITY_M0,
	IPU_F_RM_MAXLEN_M1,
	IPU_F_RM_ENDIAN_M1,
	IPU_F_RM_PRIORITY_M1,
	IPU_F_RM_MAXLEN_M2,
	IPU_F_RM_ENDIAN_M2,
	IPU_F_RM_PRIORITY_M2,
	IPU_F_RM_MAXLEN_M3,
	IPU_F_RM_ENDIAN_M3,
	IPU_F_RM_PRIORITY_M3,
	IPU_F_RM_MAXLEN_M4,
	IPU_F_RM_ENDIAN_M4,
	IPU_F_RM_PRIORITY_M4,
	IPU_F_FRAME_ID,
	IPU_F_3_OSD_COLOR_0,
	IPU_F_3_OSD_COLOR_1,
	IPU_F_3_OSD_COLOR_2,
	IPU_F_3_OSD_COLOR_3,
	IPU_F_3_OSD_COLOR_4,
	IPU_F_3_OSD_COLOR_5,
	IPU_F_3_OSD_COLOR_6,
	IPU_F_3_OSD_COLOR_7,
	IPU_F_3_OSD_COLOR_8,
	IPU_F_3_OSD_COLOR_9,
	IPU_F_3_OSD_COLOR_10,
	IPU_F_3_OSD_COLOR_11,
	IPU_F_3_OSD_COLOR_12,
	IPU_F_3_OSD_COLOR_13,
	IPU_F_3_OSD_COLOR_14,
	IPU_F_FRAME_ID_SET,
	IPU_F_FRAME_ID_EN,
	IPU_F_SRC_SEL,
	IPU_F_RD_DDR_ADDR_Y,
	IPU_F_RD_DDR_ADDR_UY,
	IPU_F_US_DDR_Y,
	IPU_F_US_DDR_UY,
	IPU_F_DS_0_DDR_Y,
	IPU_F_DS_0_DDR_UV,
	IPU_F_DS_1_DDR_Y,
	IPU_F_DS_1_DDR_UV,
	IPU_F_DS_2_DDR_Y,
	IPU_F_DS_2_DDR_UV,
	IPU_F_DS_3_DDR_Y,
	IPU_F_DS_3_DDR_UV,
	IPU_F_DS_4_DDR_Y,
	IPU_F_DS_4_DDR_UV,
	IPU_F_OSD_STA_BIN_1_NUM,
	IPU_F_OSD_STA_BIN_0_NUM,
	IPU_F_OSD_STA_BIN_3_NUM,
	IPU_F_OSD_STA_BIN_2_NUM,
	IPU_F_DDR_START,
	IPU_F_TEST_Y_SET,
	IPU_F_TEST_U_SET,
	IPU_F_TEST_V_SET,
	IPU_F_PRE_INT_1_SET,
	IPU_F_PRE_INT_0_SET,
	NUM_OF_IPU_FIELD,
};
static struct vio_field_def ipu_fields[NUM_OF_IPU_FIELD] = {
	{IPU_0_SRC_WIDTH,     IPU_F_SRC_WIDTH,  0, 13, 0},
	{IPU_0_SRC_HEIGHT,    IPU_F_SRC_HEIGHT, 0, 13, 0},
	{IPU_0_RD_DDR_STRIDE_LEN_Y, 	IPU_F_RD_DDR_STRIDE_LEN_Y,  0, 16, 0},
	{IPU_0_RD_DDR_STRIDE_LEN_UV,    IPU_F_RD_DDR_STRIDE_LEN_UV, 0, 16, 0},
	{IPU_0_US_ROI_EN,     IPU_F_US_ROI_START_Y, 	  13, 12, 0},
	{IPU_0_US_ROI_EN,     IPU_F_US_ROI_START_X, 	  1 , 12, 0},
	{IPU_0_US_ROI_EN,     IPU_F_US_ROI_EN, 			  0 , 1 , 0},
	{IPU_0_US_ROI_SIZE,   IPU_F_US_ROI_HEIGHT, 		  13, 13, 0},
	{IPU_0_US_ROI_SIZE,   IPU_F_US_ROI_WIDTH, 		  0 , 13, 0},
	{IPU_0_DS_0_ROI_EN,   IPU_F_DS_0_ROI_START_Y,	  13, 12, 0},
	{IPU_0_DS_0_ROI_EN,   IPU_F_DS_0_ROI_START_X, 	  1 , 12, 0},
	{IPU_0_DS_0_ROI_EN,   IPU_F_DS_0_ROI_EN, 		  0 , 1 , 0},
	{IPU_0_DS_0_ROI_SIZE, IPU_F_DS_0_ROI_HEIGHT, 	  13, 13, 0},
	{IPU_0_DS_0_ROI_SIZE, IPU_F_DS_0_ROI_WIDTH, 	  0 , 13, 0},
	{IPU_0_DS_1_ROI_EN,   IPU_F_DS_1_ROI_START_Y,     13, 12, 0},
	{IPU_0_DS_1_ROI_EN,   IPU_F_DS_1_ROI_START_X,     1 , 12, 0},
	{IPU_0_DS_1_ROI_EN,   IPU_F_DS_1_ROI_EN,          0 , 1 , 0},
	{IPU_0_DS_1_ROI_SIZE, IPU_F_DS_1_ROI_HEIGHT,      13, 13, 0},
	{IPU_0_DS_1_ROI_SIZE, IPU_F_DS_1_ROI_WIDTH,       0 , 13, 0},
	{IPU_0_DS_2_ROI_EN,   IPU_F_DS_2_ROI_START_Y,     13, 12, 0},
	{IPU_0_DS_2_ROI_EN,   IPU_F_DS_2_ROI_START_X,     1 , 12, 0},
	{IPU_0_DS_2_ROI_EN,   IPU_F_DS_2_ROI_EN,          0 , 1 , 0},
	{IPU_0_DS_2_ROI_SIZE, IPU_F_DS_2_ROI_HEIGHT,      13, 13, 0},
	{IPU_0_DS_2_ROI_SIZE, IPU_F_DS_2_ROI_WIDTH,       0 , 13, 0},
	{IPU_0_DS_3_ROI_EN,   IPU_F_DS_3_ROI_START_Y,     13, 12, 0},
	{IPU_0_DS_3_ROI_EN,   IPU_F_DS_3_ROI_START_X,     1 , 12, 0},
	{IPU_0_DS_3_ROI_EN,   IPU_F_DS_3_ROI_EN,          0 , 1 , 0},
	{IPU_0_DS_3_ROI_SIZE, IPU_F_DS_3_ROI_HEIGHT,      13, 13, 0},
	{IPU_0_DS_3_ROI_SIZE, IPU_F_DS_3_ROI_WIDTH,       0 , 13, 0},
	{IPU_0_DS_4_ROI_EN,   IPU_F_DS_4_ROI_START_Y,     13, 12, 0},
	{IPU_0_DS_4_ROI_EN,   IPU_F_DS_4_ROI_START_X,     1 , 12, 0},
	{IPU_0_DS_4_ROI_EN,   IPU_F_DS_4_ROI_EN,          0 , 1 , 0},
	{IPU_0_DS_4_ROI_SIZE, IPU_F_DS_4_ROI_HEIGHT,      13, 13, 0},
	{IPU_0_DS_4_ROI_SIZE, IPU_F_DS_4_ROI_WIDTH,       0 , 13, 0},
	{IPU_0_US_EN,		  IPU_F_US_TGT_HEIGHT,        14, 13, 0},
	{IPU_0_US_EN,		  IPU_F_US_TGT_WIDTH,         1 , 13, 0},
	{IPU_0_US_EN,		  IPU_F_US_EN,				  0 , 1 , 0},
	{IPU_0_US_STEP,		  IPU_F_US_STEP_Y,            13, 13, 0},
	{IPU_0_US_STEP,		  IPU_F_US_STEP_X,            0 , 13, 0},
	{IPU_0_DS_0_EN,		  IPU_F_DS_0_TGT_HEIGHT,      14, 13, 0},
	{IPU_0_DS_0_EN,		  IPU_F_DS_0_TGT_WIDTH,       1 , 13, 0},
	{IPU_0_DS_0_EN,		  IPU_F_DS_0_EN,              0 , 1 , 0},
	{IPU_0_DS_0_STEP,	  IPU_F_DS_0_PRE_Y,           30, 2 , 0},
	{IPU_0_DS_0_STEP,	  IPU_F_DS_0_PRE_X,           28, 2 , 0},
	{IPU_0_DS_0_STEP,	  IPU_F_DS_0_STEP_Y,          14, 14, 0},
	{IPU_0_DS_0_STEP,	  IPU_F_DS_0_STEP_X,          0 , 14, 0},
	{IPU_0_DS_1_EN,		  IPU_F_DS_1_TGT_HEIGHT,      14, 13, 0},
	{IPU_0_DS_1_EN,		  IPU_F_DS_1_TGT_WIDTH,       1 , 13, 0},
	{IPU_0_DS_1_EN,		  IPU_F_DS_1_EN,              0 , 1 , 0},
	{IPU_0_DS_1_STEP,	  IPU_F_DS_1_PRE_Y,           30, 2 , 0},
	{IPU_0_DS_1_STEP,	  IPU_F_DS_1_PRE_X,           28, 2 , 0},
	{IPU_0_DS_1_STEP,	  IPU_F_DS_1_STEP_Y,          14, 14, 0},
	{IPU_0_DS_1_STEP,	  IPU_F_DS_1_STEP_X,          0 , 14, 0},
	{IPU_0_DS_2_EN,		  IPU_F_DS_2_TGT_HEIGHT,      14, 13, 0},
	{IPU_0_DS_2_EN,		  IPU_F_DS_2_TGT_WIDTH,       1 , 13, 0},
	{IPU_0_DS_2_EN,		  IPU_F_DS_2_EN,              0 , 1 , 0},
	{IPU_0_DS_2_STEP,	  IPU_F_DS_2_PRE_Y,           30, 2 , 0},
	{IPU_0_DS_2_STEP,	  IPU_F_DS_2_PRE_X,           28, 2 , 0},
	{IPU_0_DS_2_STEP,	  IPU_F_DS_2_STEP_Y,          14, 14, 0},
	{IPU_0_DS_2_STEP,	  IPU_F_DS_2_STEP_X,          0 , 14, 0},
	{IPU_0_DS_3_EN,		  IPU_F_DS_3_TGT_HEIGHT,      14, 13, 0},
	{IPU_0_DS_3_EN,		  IPU_F_DS_3_TGT_WIDTH,       1 , 13, 0},
	{IPU_0_DS_3_EN,		  IPU_F_DS_3_EN,              0 , 1 , 0},
	{IPU_0_DS_3_STEP,	  IPU_F_DS_3_PRE_Y,           30, 2 , 0},
	{IPU_0_DS_3_STEP,	  IPU_F_DS_3_PRE_X,           28, 2 , 0},
	{IPU_0_DS_3_STEP,	  IPU_F_DS_3_STEP_Y,          14, 14, 0},
	{IPU_0_DS_3_STEP,	  IPU_F_DS_3_STEP_X,          0 , 14, 0},
	{IPU_0_DS_4_EN,		  IPU_F_DS_4_TGT_HEIGHT,      14, 13, 0},
	{IPU_0_DS_4_EN,		  IPU_F_DS_4_TGT_WIDTH,       1 , 13, 0},
	{IPU_0_DS_4_EN,		  IPU_F_DS_4_EN,              0 , 1 , 0},
	{IPU_0_DS_4_STEP,	  IPU_F_DS_4_PRE_Y,           30, 2 , 0},
	{IPU_0_DS_4_STEP,	  IPU_F_DS_4_PRE_X,           28, 2 , 0},
	{IPU_0_DS_4_STEP,	  IPU_F_DS_4_STEP_Y,          14, 14, 0},
	{IPU_0_DS_4_STEP,	  IPU_F_DS_4_STEP_X,          0 , 14, 0},
	{IPU_0_DS_2_EN,	  	  IPU_F_DS_2_DDR_ENABLE,       27, 1 , 0},
	{IPU_0_OSD_EN,		  IPU_F_OSD_2_OVERLAY_MODE,      15, 3 , 0},
	{IPU_0_OSD_EN,		  IPU_F_OSD_1_OVERLAY_MODE,      12, 3 , 0},
	{IPU_0_OSD_EN,		  IPU_F_OSD_0_OVERLAY_MODE,      9 , 3 , 0},
	{IPU_0_OSD_EN,		  IPU_F_OSD_2_EN,               6 , 3 , 0},
	{IPU_0_OSD_EN,		  IPU_F_OSD_1_EN,               3 , 3 , 0},
	{IPU_0_OSD_EN,		  IPU_F_OSD_0_EN,               0 , 3 , 0},
	{IPU_0_OSD_0_ROI_0_START,	IPU_F_OSD_0_ROI_0_START_Y,   12, 12, 0},
	{IPU_0_OSD_0_ROI_0_START,	IPU_F_OSD_0_ROI_0_START_X,   0 , 12, 0},
	{IPU_0_OSD_0_ROI_0_SIZE,	IPU_F_OSD_0_ROI_0_HEIGHT,    12, 12, 0},
	{IPU_0_OSD_0_ROI_0_SIZE,	IPU_F_OSD_0_ROI_0_WIDTH,     0 , 12, 0},
	{IPU_0_OSD_0_ROI_1_START,	IPU_F_OSD_0_ROI_1_START_Y,   12, 12, 0},
	{IPU_0_OSD_0_ROI_1_START,	IPU_F_OSD_0_ROI_1_START_X,   0 , 12, 0},
	{IPU_0_OSD_0_ROI_1_SIZE,	IPU_F_OSD_0_ROI_1_HEIGHT,    12, 12, 0},
	{IPU_0_OSD_0_ROI_1_SIZE,	IPU_F_OSD_0_ROI_1_WIDTH,     0 , 12, 0},
	{IPU_0_OSD_0_ROI_2_START,	IPU_F_OSD_0_ROI_2_START_Y,   12, 12, 0},
	{IPU_0_OSD_0_ROI_2_START,	IPU_F_OSD_0_ROI_2_START_X,   0 , 12, 0},
	{IPU_0_OSD_0_ROI_2_SIZE,	IPU_F_OSD_0_ROI_2_HEIGHT,    12, 12, 0},
	{IPU_0_OSD_0_ROI_2_SIZE,	IPU_F_OSD_0_ROI_2_WIDTH,     0 , 12, 0},
	{IPU_0_OSD_0_ROI_0_START,	IPU_F_OSD_1_ROI_0_START_Y,   12, 12, 0},
	{IPU_0_OSD_0_ROI_0_START,	IPU_F_OSD_1_ROI_0_START_X,   0 , 12, 0},
	{IPU_0_OSD_0_ROI_0_SIZE,	IPU_F_OSD_1_ROI_0_HEIGHT,    12, 12, 0},
	{IPU_0_OSD_0_ROI_0_SIZE,	IPU_F_OSD_1_ROI_0_WIDTH,     0 , 12, 0},
	{IPU_0_OSD_0_ROI_1_START,	IPU_F_OSD_1_ROI_1_START_Y,   12, 12, 0},
	{IPU_0_OSD_0_ROI_1_START,	IPU_F_OSD_1_ROI_1_START_X,   0 , 12, 0},
	{IPU_0_OSD_0_ROI_1_SIZE,	IPU_F_OSD_1_ROI_1_HEIGHT,    12, 12, 0},
	{IPU_0_OSD_0_ROI_1_SIZE,	IPU_F_OSD_1_ROI_1_WIDTH,     0 , 12, 0},
	{IPU_0_OSD_0_ROI_2_START,	IPU_F_OSD_1_ROI_2_START_Y,   12, 12, 0},
	{IPU_0_OSD_0_ROI_2_START,	IPU_F_OSD_1_ROI_2_START_X,   0 , 12, 0},
	{IPU_0_OSD_0_ROI_2_SIZE,	IPU_F_OSD_1_ROI_2_HEIGHT,    12, 12, 0},
	{IPU_0_OSD_0_ROI_2_SIZE,	IPU_F_OSD_1_ROI_2_WIDTH,     0 , 12, 0},
	{IPU_0_OSD_0_ROI_0_START,	IPU_F_OSD_2_ROI_0_START_Y,   12, 12, 0},
	{IPU_0_OSD_0_ROI_0_START,	IPU_F_OSD_2_ROI_0_START_X,   0 , 12, 0},
	{IPU_0_OSD_0_ROI_0_SIZE,	IPU_F_OSD_2_ROI_0_HEIGHT,    12, 12, 0},
	{IPU_0_OSD_0_ROI_0_SIZE,	IPU_F_OSD_2_ROI_0_WIDTH,     0 , 12, 0},
	{IPU_0_OSD_0_ROI_1_START,	IPU_F_OSD_2_ROI_1_START_Y,   12, 12, 0},
	{IPU_0_OSD_0_ROI_1_START,	IPU_F_OSD_2_ROI_1_START_X,   0 , 12, 0},
	{IPU_0_OSD_0_ROI_1_SIZE,	IPU_F_OSD_2_ROI_1_HEIGHT,    12, 12, 0},
	{IPU_0_OSD_0_ROI_1_SIZE,	IPU_F_OSD_2_ROI_1_WIDTH,     0 , 12, 0},
	{IPU_0_OSD_0_ROI_2_START,	IPU_F_OSD_2_ROI_2_START_Y,   12, 12, 0},
	{IPU_0_OSD_0_ROI_2_START,	IPU_F_OSD_2_ROI_2_START_X,   0 , 12, 0},
	{IPU_0_OSD_0_ROI_2_SIZE,	IPU_F_OSD_2_ROI_2_HEIGHT,    12, 12, 0},
	{IPU_0_OSD_0_ROI_2_SIZE,	IPU_F_OSD_2_ROI_2_WIDTH,     0 , 12, 0},
	{IPU_0_OSD_STA_ENABLE,		IPU_F_OSD_2_STA_ENABLE,      16, 8 , 0},
	{IPU_0_OSD_STA_ENABLE,		IPU_F_OSD_1_STA_ENABLE,      8 , 8 , 0},
	{IPU_0_OSD_STA_ENABLE,		IPU_F_OSD_0_STA_ENABLE,      0 , 8 , 0},
	{IPU_0_OSD_0_STA_ROI_0_START,	IPU_F_OSD_0_STA_ROI_0_START_Y, 12, 12, 0},
	{IPU_0_OSD_0_STA_ROI_0_START,	IPU_F_OSD_0_STA_ROI_0_START_X, 0 , 12, 0},
	{IPU_0_OSD_0_STA_ROI_0_SIZE,	IPU_F_OSD_0_STA_ROI_0_HEIGHT,  8 , 8 , 0},
	{IPU_0_OSD_0_STA_ROI_0_SIZE,	IPU_F_OSD_0_STA_ROI_0_WIDTH,   0 , 8 , 0},
	{IPU_0_OSD_0_STA_ROI_1_START,	IPU_F_OSD_0_STA_ROI_1_START_Y, 12, 12, 0},
	{IPU_0_OSD_0_STA_ROI_1_START,	IPU_F_OSD_0_STA_ROI_1_START_X, 0 , 12, 0},
	{IPU_0_OSD_0_STA_ROI_1_SIZE,	IPU_F_OSD_0_STA_ROI_1_HEIGHT,  8 , 8 , 0},
	{IPU_0_OSD_0_STA_ROI_1_SIZE,	IPU_F_OSD_0_STA_ROI_1_WIDTH,   0 , 8 , 0},
	{IPU_0_OSD_0_STA_ROI_2_START,	IPU_F_OSD_0_STA_ROI_2_START_Y, 12, 12, 0},
	{IPU_0_OSD_0_STA_ROI_2_START,	IPU_F_OSD_0_STA_ROI_2_START_X, 0 , 12, 0},
	{IPU_0_OSD_0_STA_ROI_2_SIZE,	IPU_F_OSD_0_STA_ROI_2_HEIGHT,  8 , 8 , 0},
	{IPU_0_OSD_0_STA_ROI_2_SIZE,	IPU_F_OSD_0_STA_ROI_2_WIDTH,   0 , 8 , 0},
	{IPU_0_OSD_0_STA_ROI_3_START,	IPU_F_OSD_0_STA_ROI_3_START_Y, 12, 12, 0},
	{IPU_0_OSD_0_STA_ROI_3_START,	IPU_F_OSD_0_STA_ROI_3_START_X, 0 , 12, 0},
	{IPU_0_OSD_0_STA_ROI_3_SIZE,	IPU_F_OSD_0_STA_ROI_3_HEIGHT,  8 , 8 , 0},
	{IPU_0_OSD_0_STA_ROI_3_SIZE,	IPU_F_OSD_0_STA_ROI_3_WIDTH,   0 , 8 , 0},
	{IPU_0_OSD_0_STA_ROI_4_START,	IPU_F_OSD_0_STA_ROI_4_START_Y, 12, 12, 0},
	{IPU_0_OSD_0_STA_ROI_4_START,	IPU_F_OSD_0_STA_ROI_4_START_X, 0 , 12, 0},
	{IPU_0_OSD_0_STA_ROI_4_SIZE,	IPU_F_OSD_0_STA_ROI_4_HEIGHT,  8 , 8 , 0},
	{IPU_0_OSD_0_STA_ROI_4_SIZE,	IPU_F_OSD_0_STA_ROI_4_WIDTH,   0 , 8 , 0},
	{IPU_0_OSD_0_STA_ROI_5_START,	IPU_F_OSD_0_STA_ROI_5_START_Y, 12, 12, 0},
	{IPU_0_OSD_0_STA_ROI_5_START,	IPU_F_OSD_0_STA_ROI_5_START_X, 0 , 12, 0},
	{IPU_0_OSD_0_STA_ROI_5_SIZE,	IPU_F_OSD_0_STA_ROI_5_HEIGHT,  8 , 8 , 0},
	{IPU_0_OSD_0_STA_ROI_5_SIZE,	IPU_F_OSD_0_STA_ROI_5_WIDTH,   0 , 8 , 0},
	{IPU_0_OSD_0_STA_ROI_6_START,	IPU_F_OSD_0_STA_ROI_6_START_Y, 12, 12, 0},
	{IPU_0_OSD_0_STA_ROI_6_START,	IPU_F_OSD_0_STA_ROI_6_START_X, 0 , 12, 0},
	{IPU_0_OSD_0_STA_ROI_6_SIZE,	IPU_F_OSD_0_STA_ROI_6_HEIGHT,  8 , 8 , 0},
	{IPU_0_OSD_0_STA_ROI_6_SIZE,	IPU_F_OSD_0_STA_ROI_6_WIDTH,   0 , 8 , 0},
	{IPU_0_OSD_0_STA_ROI_7_START,	IPU_F_OSD_0_STA_ROI_7_START_Y, 12, 12, 0},
	{IPU_0_OSD_0_STA_ROI_7_START,	IPU_F_OSD_0_STA_ROI_7_START_X, 0 , 12, 0},
	{IPU_0_OSD_0_STA_ROI_7_SIZE,	IPU_F_OSD_0_STA_ROI_7_HEIGHT,  8 , 8 , 0},
	{IPU_0_OSD_0_STA_ROI_7_SIZE,	IPU_F_OSD_0_STA_ROI_7_WIDTH,   0 , 8 , 0},
	{IPU_0_OSD_1_STA_ROI_0_START,	IPU_F_OSD_1_STA_ROI_0_START_Y, 12, 12, 0},
	{IPU_0_OSD_1_STA_ROI_0_START,	IPU_F_OSD_1_STA_ROI_0_START_X, 0 , 12, 0},
	{IPU_0_OSD_1_STA_ROI_0_SIZE,	IPU_F_OSD_1_STA_ROI_0_HEIGHT,  8 , 8 , 0},
	{IPU_0_OSD_1_STA_ROI_0_SIZE,	IPU_F_OSD_1_STA_ROI_0_WIDTH,   0 , 8 , 0},
	{IPU_0_OSD_1_STA_ROI_1_START,	IPU_F_OSD_1_STA_ROI_1_START_Y, 12, 12, 0},
	{IPU_0_OSD_1_STA_ROI_1_START,	IPU_F_OSD_1_STA_ROI_1_START_X, 0 , 12, 0},
	{IPU_0_OSD_1_STA_ROI_1_SIZE,	IPU_F_OSD_1_STA_ROI_1_HEIGHT,  8 , 8 , 0},
	{IPU_0_OSD_1_STA_ROI_1_SIZE,	IPU_F_OSD_1_STA_ROI_1_WIDTH,   0 , 8 , 0},
	{IPU_0_OSD_1_STA_ROI_2_START,	IPU_F_OSD_1_STA_ROI_2_START_Y, 12, 12, 0},
	{IPU_0_OSD_1_STA_ROI_2_START,	IPU_F_OSD_1_STA_ROI_2_START_X, 0 , 12, 0},
	{IPU_0_OSD_1_STA_ROI_2_SIZE,	IPU_F_OSD_1_STA_ROI_2_HEIGHT,  8 , 8 , 0},
	{IPU_0_OSD_1_STA_ROI_2_SIZE,	IPU_F_OSD_1_STA_ROI_2_WIDTH,   0 , 8 , 0},
	{IPU_0_OSD_1_STA_ROI_3_START,	IPU_F_OSD_1_STA_ROI_3_START_Y, 12, 12, 0},
	{IPU_0_OSD_1_STA_ROI_3_START,	IPU_F_OSD_1_STA_ROI_3_START_X, 0 , 12, 0},
	{IPU_0_OSD_1_STA_ROI_3_SIZE,	IPU_F_OSD_1_STA_ROI_3_HEIGHT,  8 , 8 , 0},
	{IPU_0_OSD_1_STA_ROI_3_SIZE,	IPU_F_OSD_1_STA_ROI_3_WIDTH,   0 , 8 , 0},
	{IPU_0_OSD_1_STA_ROI_4_START,	IPU_F_OSD_1_STA_ROI_4_START_Y, 12, 12, 0},
	{IPU_0_OSD_1_STA_ROI_4_START,	IPU_F_OSD_1_STA_ROI_4_START_X, 0 , 12, 0},
	{IPU_0_OSD_1_STA_ROI_4_SIZE,	IPU_F_OSD_1_STA_ROI_4_HEIGHT,  8 , 8 , 0},
	{IPU_0_OSD_1_STA_ROI_4_SIZE,	IPU_F_OSD_1_STA_ROI_4_WIDTH,   0 , 8 , 0},
	{IPU_0_OSD_1_STA_ROI_5_START,	IPU_F_OSD_1_STA_ROI_5_START_Y, 12, 12, 0},
	{IPU_0_OSD_1_STA_ROI_5_START,	IPU_F_OSD_1_STA_ROI_5_START_X, 0 , 12, 0},
	{IPU_0_OSD_1_STA_ROI_5_SIZE,	IPU_F_OSD_1_STA_ROI_5_HEIGHT,  8 , 8 , 0},
	{IPU_0_OSD_1_STA_ROI_5_SIZE,	IPU_F_OSD_1_STA_ROI_5_WIDTH,   0 , 8 , 0},
	{IPU_0_OSD_1_STA_ROI_6_START,	IPU_F_OSD_1_STA_ROI_6_START_Y, 12, 12, 0},
	{IPU_0_OSD_1_STA_ROI_6_START,	IPU_F_OSD_1_STA_ROI_6_START_X, 0 , 12, 0},
	{IPU_0_OSD_1_STA_ROI_6_SIZE,	IPU_F_OSD_1_STA_ROI_6_HEIGHT,  8 , 8 , 0},
	{IPU_0_OSD_1_STA_ROI_6_SIZE,	IPU_F_OSD_1_STA_ROI_6_WIDTH,   0 , 8 , 0},
	{IPU_0_OSD_1_STA_ROI_7_START,	IPU_F_OSD_1_STA_ROI_7_START_Y, 12, 12, 0},
	{IPU_0_OSD_1_STA_ROI_7_START,	IPU_F_OSD_1_STA_ROI_7_START_X, 0 , 12, 0},
	{IPU_0_OSD_1_STA_ROI_7_SIZE,	IPU_F_OSD_1_STA_ROI_7_HEIGHT,  8 , 8 , 0},
	{IPU_0_OSD_1_STA_ROI_7_SIZE,	IPU_F_OSD_1_STA_ROI_7_WIDTH,   0 , 8 , 0},
	{IPU_0_OSD_2_STA_ROI_0_START,	IPU_F_OSD_2_STA_ROI_0_START_Y, 12, 12, 0},
	{IPU_0_OSD_2_STA_ROI_0_START,	IPU_F_OSD_2_STA_ROI_0_START_X, 0 , 12, 0},
	{IPU_0_OSD_2_STA_ROI_0_SIZE,	IPU_F_OSD_2_STA_ROI_0_HEIGHT,  8 , 8 , 0},
	{IPU_0_OSD_2_STA_ROI_0_SIZE,	IPU_F_OSD_2_STA_ROI_0_WIDTH,   0 , 8 , 0},
	{IPU_0_OSD_2_STA_ROI_1_START,	IPU_F_OSD_2_STA_ROI_1_START_Y, 12, 12, 0},
	{IPU_0_OSD_2_STA_ROI_1_START,	IPU_F_OSD_2_STA_ROI_1_START_X, 0 , 12, 0},
	{IPU_0_OSD_2_STA_ROI_1_SIZE,	IPU_F_OSD_2_STA_ROI_1_HEIGHT,  8 , 8 , 0},
	{IPU_0_OSD_2_STA_ROI_1_SIZE,	IPU_F_OSD_2_STA_ROI_1_WIDTH,   0 , 8 , 0},
	{IPU_0_OSD_2_STA_ROI_2_START,	IPU_F_OSD_2_STA_ROI_2_START_Y, 12, 12, 0},
	{IPU_0_OSD_2_STA_ROI_2_START,	IPU_F_OSD_2_STA_ROI_2_START_X, 0 , 12, 0},
	{IPU_0_OSD_2_STA_ROI_2_SIZE,	IPU_F_OSD_2_STA_ROI_2_HEIGHT,  8 , 8 , 0},
	{IPU_0_OSD_2_STA_ROI_2_SIZE,	IPU_F_OSD_2_STA_ROI_2_WIDTH,   0 , 8 , 0},
	{IPU_0_OSD_2_STA_ROI_3_START,	IPU_F_OSD_2_STA_ROI_3_START_Y, 12, 12, 0},
	{IPU_0_OSD_2_STA_ROI_3_START,	IPU_F_OSD_2_STA_ROI_3_START_X, 0 , 12, 0},
	{IPU_0_OSD_2_STA_ROI_3_SIZE,	IPU_F_OSD_2_STA_ROI_3_HEIGHT,  8 , 8 , 0},
	{IPU_0_OSD_2_STA_ROI_3_SIZE,	IPU_F_OSD_2_STA_ROI_3_WIDTH,   0 , 8 , 0},
	{IPU_0_OSD_2_STA_ROI_4_START,	IPU_F_OSD_2_STA_ROI_4_START_Y, 12, 12, 0},
	{IPU_0_OSD_2_STA_ROI_4_START,	IPU_F_OSD_2_STA_ROI_4_START_X, 0 , 12, 0},
	{IPU_0_OSD_2_STA_ROI_4_SIZE,	IPU_F_OSD_2_STA_ROI_4_HEIGHT,  8 , 8 , 0},
	{IPU_0_OSD_2_STA_ROI_4_SIZE,	IPU_F_OSD_2_STA_ROI_4_WIDTH,   0 , 8 , 0},
	{IPU_0_OSD_2_STA_ROI_5_START,	IPU_F_OSD_2_STA_ROI_5_START_Y, 12, 12, 0},
	{IPU_0_OSD_2_STA_ROI_5_START,	IPU_F_OSD_2_STA_ROI_5_START_X, 0 , 12, 0},
	{IPU_0_OSD_2_STA_ROI_5_SIZE,	IPU_F_OSD_2_STA_ROI_5_HEIGHT,  8 , 8 , 0},
	{IPU_0_OSD_2_STA_ROI_5_SIZE,	IPU_F_OSD_2_STA_ROI_5_WIDTH,   0 , 8 , 0},
	{IPU_0_OSD_2_STA_ROI_6_START,	IPU_F_OSD_2_STA_ROI_6_START_Y, 12, 12, 0},
	{IPU_0_OSD_2_STA_ROI_6_START,	IPU_F_OSD_2_STA_ROI_6_START_X, 0 , 12, 0},
	{IPU_0_OSD_2_STA_ROI_6_SIZE,	IPU_F_OSD_2_STA_ROI_6_HEIGHT,  8 , 8 , 0},
	{IPU_0_OSD_2_STA_ROI_6_SIZE,	IPU_F_OSD_2_STA_ROI_6_WIDTH,   0 , 8 , 0},
	{IPU_0_OSD_2_STA_ROI_7_START,	IPU_F_OSD_2_STA_ROI_7_START_Y, 12, 12, 0},
	{IPU_0_OSD_2_STA_ROI_7_START,	IPU_F_OSD_2_STA_ROI_7_START_X, 0 , 12, 0},
	{IPU_0_OSD_2_STA_ROI_7_SIZE,	IPU_F_OSD_2_STA_ROI_7_HEIGHT,  8 , 8 , 0},
	{IPU_0_OSD_2_STA_ROI_7_SIZE,	IPU_F_OSD_2_STA_ROI_7_WIDTH,   0 , 8 , 0},
	{IPU_0_OSD_STA_LEVEL,		IPU_F_OSD_STA_LEVEL_2,   16, 8 , 0},
	{IPU_0_OSD_STA_LEVEL,		IPU_F_OSD_STA_LEVEL_1,   8 , 8 , 0},
	{IPU_0_OSD_STA_LEVEL,		IPU_F_OSD_STA_LEVEL_0,   0 , 8 , 0},
	{IPU_0_OSD_0_ROI_0_ADDR,	IPU_F_OSD_0_ROI_0_ADDR,  0 , 32, 0},
	{IPU_0_OSD_0_ROI_1_ADDR,	IPU_F_OSD_0_ROI_1_ADDR,  0 , 32, 0},
	{IPU_0_OSD_0_ROI_2_ADDR,	IPU_F_OSD_0_ROI_2_ADDR,  0 , 32, 0},
	{IPU_0_OSD_1_ROI_0_ADDR,	IPU_F_OSD_1_ROI_0_ADDR,  0 , 32, 0},
	{IPU_0_OSD_1_ROI_1_ADDR,	IPU_F_OSD_1_ROI_1_ADDR,  0 , 32, 0},
	{IPU_0_OSD_1_ROI_2_ADDR,	IPU_F_OSD_1_ROI_2_ADDR,  0 , 32, 0},
	{IPU_0_OSD_2_ROI_0_ADDR,	IPU_F_OSD_2_ROI_0_ADDR,  0 , 32, 0},
	{IPU_0_OSD_2_ROI_1_ADDR,	IPU_F_OSD_2_ROI_1_ADDR,  0 , 32, 0},
	{IPU_0_OSD_2_ROI_2_ADDR,	IPU_F_OSD_2_ROI_2_ADDR,  0 , 32, 0},
	{IPU_0_US_DDR_STRIDE_LEN_Y,		IPU_F_US_DDR_STRIDE_LEN_Y,     0 ,16, 0},
	{IPU_0_US_DDR_STRIDE_LEN_UV,	IPU_F_US_DDR_STRIDE_LEN_UV,    0 ,16, 0},
	{IPU_0_DS_0_DDR_STRIDE_LEN_Y,	IPU_F_DS_0_DDR_STRIDE_LEN_Y,   0 ,16, 0},
	{IPU_0_DS_0_DDR_STRIDE_LEN_UV,	IPU_F_DS_0_DDR_STRIDE_LEN_UV,  0 ,16, 0},
	{IPU_0_DS_1_DDR_STRIDE_LEN_Y,	IPU_F_DS_1_DDR_STRIDE_LEN_Y,   0 ,16, 0},
	{IPU_0_DS_1_DDR_STRIDE_LEN_UV,	IPU_F_DS_1_DDR_STRIDE_LEN_UV,  0 ,16, 0},
	{IPU_0_DS_2_DDR_STRIDE_LEN_Y,	IPU_F_DS_2_DDR_STRIDE_LEN_Y,   0 ,16, 0},
	{IPU_0_DS_2_DDR_STRIDE_LEN_UV,	IPU_F_DS_2_DDR_STRIDE_LEN_UV,  0 ,16, 0},
	{IPU_0_DS_3_DDR_STRIDE_LEN_Y,	IPU_F_DS_3_DDR_STRIDE_LEN_Y,   0 ,16, 0},
	{IPU_0_DS_3_DDR_STRIDE_LEN_UV,	IPU_F_DS_3_DDR_STRIDE_LEN_UV,  0 ,16, 0},
	{IPU_0_DS_4_DDR_STRIDE_LEN_Y,	IPU_F_DS_4_DDR_STRIDE_LEN_Y,   0 ,16, 0},
	{IPU_0_DS_4_DDR_STRIDE_LEN_UV,	IPU_F_DS_4_DDR_STRIDE_LEN_UV,  0 ,16, 0},
	{IPU_SIZE_ERR,		IPU_F_SIZE_ERR_H,    12, 12, 0},
	{IPU_SIZE_ERR,		IPU_F_SIZE_ERR_W,    0 , 12, 0},
	{IPU_CHECKSUM_Y,	IPU_F_CHECKSUM_Y,    0 , 32, 0},
	{IPU_CHECKSUM_UV,	IPU_F_CHECKSUM_UV,   0 , 32, 0},
	{IPU_SCALE_STATE,	IPU_F_LAYER_0_US_ACTIVE,	27, 1 , 0},
	{IPU_SCALE_STATE,	IPU_F_LAYER_2_DS_ACTIVE,    22, 5 , 0},
	{IPU_SCALE_STATE,	IPU_F_LAYER_1_DS_ACTIVE,    17, 5 , 0},
	{IPU_SCALE_STATE,	IPU_F_LAYER_0_DS_ACTIVE,    12, 5 , 0},
	{IPU_SCALE_STATE,	IPU_F_LAYER_2_STATE,        8 , 4 , 0},
	{IPU_SCALE_STATE,	IPU_F_LAYER_1_STATE,        4 , 4 , 0},
	{IPU_SCALE_STATE,	IPU_F_LAYER_0_STATE,        0 , 4 , 0},
	{IPU_LAYER_0_WR_RD_LINE_CNT,	IPU_F_LAYER_0_RD_CNT,		16, 13, 0},
	{IPU_LAYER_0_WR_RD_LINE_CNT,	IPU_F_LAYER_0_WR_LINE_CNT,  0 , 13, 0},
	{IPU_LAYER_1_WR_RD_LINE_CNT,	IPU_F_LAYER_1_RD_CNT,       16, 13, 0},
	{IPU_LAYER_1_WR_RD_LINE_CNT,	IPU_F_LAYER_1_WR_LINE_CNT,  0 , 13, 0},
	{IPU_LAYER_2_WR_RD_LINE_CNT,	IPU_F_LAYER_2_RD_CNT,       16, 13, 0},
	{IPU_LAYER_2_WR_RD_LINE_CNT,	IPU_F_LAYER_2_WR_LINE_CNT,  0 , 13, 0},
	{IPU_LAYER_0_REQ_LINE_CNT,		IPU_F_LAYER_0_REQ_LINE_CNT, 0 , 13, 0},
	{IPU_LAYER_1_REQ_LINE_CNT,		IPU_F_LAYER_1_REQ_LINE_CNT, 0 , 13, 0},
	{IPU_LAYER_2_REQ_LINE_CNT,		IPU_F_LAYER_2_REQ_LINE_CNT, 0 , 13, 0},
	{IPU_ERR_CLR,		IPU_F_LINE_DELAY_SET,	1 , 8 , 0},
	{IPU_ERR_CLR,		IPU_F_ERR_CLR,          0 , 1 , 0},
	{IPU_ERR_STATUS,	IPU_F_BUF_ERR,          2 , 1 , 0},
	{IPU_ERR_STATUS,	IPU_F_STA_SIZE_ERR_H,       1 , 1 , 0},
	{IPU_ERR_STATUS,	IPU_F_STA_SIZE_ERR_W,       0 , 1 , 0},
	{IPU_WR_DDR_FIFO_THRED_1,	IPU_F_WD_DDR_FIFO_THRED_5,       0 , 8 , 32},
	/*0xe50*/
	{IPU_INT_MASK,		IPU_F_PRE_INT_1_ENABLE,		18, 1 , 1},
	{IPU_INT_MASK,		IPU_F_PRE_INT_0_ENABLE, 	17, 1 , 1},
	{IPU_INT_MASK,		IPU_F_OSD_2_DROP_ENABLE,	16, 1 , 1},
	{IPU_INT_MASK,		IPU_F_OSD_1_DROP_ENABLE,	15, 1 , 1},
	{IPU_INT_MASK,		IPU_F_OSD_0_DROP_ENABLE,	14, 1 , 1},
	{IPU_INT_MASK,		IPU_F_DS_4_DROP_ENABLE, 	13, 1 , 1},
	{IPU_INT_MASK,		IPU_F_DS_3_DROP_ENABLE, 	12, 1 , 1},
	{IPU_INT_MASK,		IPU_F_DS_2_DROP_ENABLE, 	11, 1 , 1},
	{IPU_INT_MASK,		IPU_F_DS_1_DROP_ENABLE, 	10, 1 , 1},
	{IPU_INT_MASK,		IPU_F_DS_0_DROP_ENABLE, 	 9, 1 , 1},
	{IPU_INT_MASK,		IPU_F_US_DROP_ENABLE,   	 8, 1 , 1},
	{IPU_INT_MASK,		IPU_F_DS_4_DONE_ENABLE, 	 7, 1 , 1},
	{IPU_INT_MASK,		IPU_F_DS_3_DONE_ENABLE, 	 6, 1 , 1},
	{IPU_INT_MASK,		IPU_F_DS_2_DONE_ENABLE, 	 5, 1 , 1},
	{IPU_INT_MASK,		IPU_F_DS_1_DONE_ENABLE, 	 4, 1 , 1},
	{IPU_INT_MASK,		IPU_F_DS_0_DONE_ENABLE, 	 3, 1 , 1},
	{IPU_INT_MASK,		IPU_F_US_DONE_ENABLE,   	 2, 1 , 1},
	{IPU_INT_MASK,		IPU_F_FRAME_DONE_ENABLE,	 1, 1 , 1},
	{IPU_INT_MASK,		IPU_F_FRAME_START_ENABLE,	 0, 1 , 1},
	{IPU_INT_STATUS,	IPU_F_PRE_INT_1_DONE,       18, 1 , 0},
	{IPU_INT_STATUS,	IPU_F_PRE_INT_0_DONE,       17, 1 , 0},
	{IPU_INT_STATUS,	IPU_F_OSD_2_DROP,           16, 1 , 0},
	{IPU_INT_STATUS,	IPU_F_OSD_1_DROP,           15, 1 , 0},
	{IPU_INT_STATUS,	IPU_F_OSD_0_DROP,           14, 1 , 0},
	{IPU_INT_STATUS,	IPU_F_DS_4_DROP,            13, 1 , 0},
	{IPU_INT_STATUS,	IPU_F_DS_3_DROP,            12, 1 , 0},
	{IPU_INT_STATUS,	IPU_F_DS_2_DROP,            11, 1 , 0},
	{IPU_INT_STATUS,	IPU_F_DS_1_DROP,            10, 1 , 0},
	{IPU_INT_STATUS,	IPU_F_DS_0_DROP,             9, 1 , 0},
	{IPU_INT_STATUS,	IPU_F_US_DROP,               8, 1 , 0},
	{IPU_INT_STATUS,	IPU_F_DS_4_DONE,             7, 1 , 0},
	{IPU_INT_STATUS,	IPU_F_DS_3_DONE,             6, 1 , 0},
	{IPU_INT_STATUS,	IPU_F_DS_2_DONE,             5, 1 , 0},
	{IPU_INT_STATUS,	IPU_F_DS_1_DONE,             4, 1 , 0},
	{IPU_INT_STATUS,	IPU_F_DS_0_DONE,             3, 1 , 0},
	{IPU_INT_STATUS,	IPU_F_US_DONE,               2, 1 , 0},
	{IPU_INT_STATUS,	IPU_F_FRAME_DONE,            1, 1 , 0},
	{IPU_INT_STATUS,	IPU_F_FRAME_START,           0, 1 , 0},
	{IPU_CFG_RDY,		IPU_F_SHD_RDY_COMMON,        4, 1 , 0},
	{IPU_CFG_RDY,		IPU_F_SHD_RDY_3,             3, 1 , 0},
	{IPU_CFG_RDY,		IPU_F_SHD_RDY_2,             2, 1 , 0},
	{IPU_CFG_RDY,		IPU_F_SHD_RDY_1,             1, 1 , 0},
	{IPU_CFG_RDY,		IPU_F_SHD_RDY_0,             0, 1 , 0},
	{IPU_CFG_SEL,		IPU_F_CFG_SEL,               0, 2 , 0},
	{IPU_BUS_CFG,		IPU_F_AXI_ID,                0, 4 , 0},
	{IPU_BUS_CTRL_WM_0,		IPU_F_WM_MAXLEN_M0,      8, 8 , 0},
	{IPU_BUS_CTRL_WM_0,		IPU_F_WM_ENDIAN_M0,      4, 4 , 0},
	{IPU_BUS_CTRL_WM_0,		IPU_F_WM_PRIORITY_M0,    0, 4 , 0},
	{IPU_BUS_CTRL_WM_1,		IPU_F_WM_MAXLEN_M1,      8, 8 , 0},
	{IPU_BUS_CTRL_WM_1,		IPU_F_WM_ENDIAN_M1,      4, 4 , 0},
	{IPU_BUS_CTRL_WM_1,		IPU_F_WM_PRIORITY_M1,    0, 4 , 0},
	{IPU_BUS_CTRL_WM_2,		IPU_F_WM_MAXLEN_M2,      8, 8 , 0},
	{IPU_BUS_CTRL_WM_2,		IPU_F_WM_ENDIAN_M2,      4, 4 , 0},
	{IPU_BUS_CTRL_WM_2,		IPU_F_WM_PRIORITY_M2,    0, 4 , 0},
	{IPU_BUS_CTRL_WM_3,		IPU_F_WM_MAXLEN_M3,      8, 8 , 0},
	{IPU_BUS_CTRL_WM_3,		IPU_F_WM_ENDIAN_M3,      4, 4 , 0},
	{IPU_BUS_CTRL_WM_3,		IPU_F_WM_PRIORITY_M3,    0, 4 , 0},
	{IPU_BUS_CTRL_WM_4,		IPU_F_WM_MAXLEN_M4,      8, 8 , 0},
	{IPU_BUS_CTRL_WM_4,		IPU_F_WM_ENDIAN_M4,      4, 4 , 0},
	{IPU_BUS_CTRL_WM_4,		IPU_F_WM_PRIORITY_M4,    0, 4 , 0},
	{IPU_BUS_CTRL_WM_5,		IPU_F_WM_MAXLEN_M5,      8, 8 , 0},
	{IPU_BUS_CTRL_WM_5,		IPU_F_WM_ENDIAN_M5,      4, 4 , 0},
	{IPU_BUS_CTRL_WM_5,		IPU_F_WM_PRIORITY_M5,    0, 4 , 0},
	{IPU_BUS_CTRL_WM_6,		IPU_F_WM_MAXLEN_M6,      8, 8 , 0},
	{IPU_BUS_CTRL_WM_6,		IPU_F_WM_ENDIAN_M6,      4, 4 , 0},
	{IPU_BUS_CTRL_WM_6,		IPU_F_WM_PRIORITY_M6,    0, 4 , 0},
	{IPU_BUS_CTRL_WM_7,		IPU_F_WM_MAXLEN_M7,      8, 8 , 0},
	{IPU_BUS_CTRL_WM_7,		IPU_F_WM_ENDIAN_M7,      4, 4 , 0},
	{IPU_BUS_CTRL_WM_7,		IPU_F_WM_PRIORITY_M7,    0, 4 , 0},
	{IPU_BUS_CTRL_WM_8,		IPU_F_WM_MAXLEN_M8,      8, 8 , 0},
	{IPU_BUS_CTRL_WM_8,		IPU_F_WM_ENDIAN_M8,      4, 4 , 0},
	{IPU_BUS_CTRL_WM_8,		IPU_F_WM_PRIORITY_M8,    0, 4 , 0},
	{IPU_BUS_CTRL_WM_9,		IPU_F_WM_MAXLEN_M9,      8, 8 , 0},
	{IPU_BUS_CTRL_WM_9,		IPU_F_WM_ENDIAN_M9,      4, 4 , 0},
	{IPU_BUS_CTRL_WM_9,		IPU_F_WM_PRIORITY_M9,    0, 4 , 0},
	{IPU_BUS_CTRL_WM_10,	IPU_F_WM_MAXLEN_M10,     8, 8 , 0},
	{IPU_BUS_CTRL_WM_10,	IPU_F_WM_ENDIAN_M10,     4, 4 , 0},
	{IPU_BUS_CTRL_WM_10,	IPU_F_WM_PRIORITY_M10,   0, 4 , 0},
	{IPU_BUS_CTRL_WM_11,	IPU_F_WM_MAXLEN_M11,     8, 8 , 0},
	{IPU_BUS_CTRL_WM_11,	IPU_F_WM_ENDIAN_M11,     4, 4 , 0},
	{IPU_BUS_CTRL_WM_11,	IPU_F_WM_PRIORITY_M11,   0, 4 , 0},
	{IPU_BUS_CTRL_WM_12,	IPU_F_WM_MAXLEN_M12,     8, 8 , 0},
	{IPU_BUS_CTRL_WM_12,	IPU_F_WM_ENDIAN_M12,     4, 4 , 0},
	{IPU_BUS_CTRL_WM_12,	IPU_F_WM_PRIORITY_M12,   0, 4 , 0},
	{IPU_BUS_CTRL_RM_0,		IPU_F_RM_MAXLEN_M0,      8, 8 , 0},
	{IPU_BUS_CTRL_RM_0,		IPU_F_RM_ENDIAN_M0,      4, 4 , 0},
	{IPU_BUS_CTRL_RM_0,		IPU_F_RM_PRIORITY_M0,    0, 4 , 0},
	{IPU_BUS_CTRL_RM_1,		IPU_F_RM_MAXLEN_M1,      8, 8 , 0},
	{IPU_BUS_CTRL_RM_1,		IPU_F_RM_ENDIAN_M1,      4, 4 , 0},
	{IPU_BUS_CTRL_RM_1,		IPU_F_RM_PRIORITY_M1,    0, 4 , 0},
	{IPU_BUS_CTRL_RM_2,		IPU_F_RM_MAXLEN_M2,      8, 8 , 0},
	{IPU_BUS_CTRL_RM_2,		IPU_F_RM_ENDIAN_M2,      4, 4 , 0},
	{IPU_BUS_CTRL_RM_2,		IPU_F_RM_PRIORITY_M2,    0, 4 , 0},
	{IPU_BUS_CTRL_RM_3,		IPU_F_RM_MAXLEN_M3,      8, 8 , 0},
	{IPU_BUS_CTRL_RM_3,		IPU_F_RM_ENDIAN_M3,      4, 4 , 0},
	{IPU_BUS_CTRL_RM_3,		IPU_F_RM_PRIORITY_M3,    0, 4 , 0},
	{IPU_BUS_CTRL_RM_4,		IPU_F_RM_MAXLEN_M4,      8, 8 , 0},
	{IPU_BUS_CTRL_RM_4,		IPU_F_RM_ENDIAN_M4,      4, 4 , 0},
	{IPU_BUS_CTRL_RM_4,		IPU_F_RM_PRIORITY_M4,    0, 4 , 0},
	{IPU_FRAME_ID,			IPU_F_FRAME_ID,          0, 16, 0},
	{IPU_OSD_COLOR_0,		IPU_F_3_OSD_COLOR_0,     0, 24, 0},
	{IPU_OSD_COLOR_1,		IPU_F_3_OSD_COLOR_1,     0, 24, 0},
	{IPU_OSD_COLOR_2,		IPU_F_3_OSD_COLOR_2,     0, 24, 0},
	{IPU_OSD_COLOR_3,		IPU_F_3_OSD_COLOR_3,     0, 24, 0},
	{IPU_OSD_COLOR_4,		IPU_F_3_OSD_COLOR_4,     0, 24, 0},
	{IPU_OSD_COLOR_5,		IPU_F_3_OSD_COLOR_5,     0, 24, 0},
	{IPU_OSD_COLOR_6,		IPU_F_3_OSD_COLOR_6,     0, 24, 0},
	{IPU_OSD_COLOR_7,		IPU_F_3_OSD_COLOR_7,     0, 24, 0},
	{IPU_OSD_COLOR_8,		IPU_F_3_OSD_COLOR_8,     0, 24, 0},
	{IPU_OSD_COLOR_9,		IPU_F_3_OSD_COLOR_9,     0, 24, 0},
	{IPU_OSD_COLOR_10,		IPU_F_3_OSD_COLOR_10,    0, 24, 0},
	{IPU_OSD_COLOR_11,		IPU_F_3_OSD_COLOR_11,    0, 24, 0},
	{IPU_OSD_COLOR_12,		IPU_F_3_OSD_COLOR_12,    0, 24, 0},
	{IPU_OSD_COLOR_13,		IPU_F_3_OSD_COLOR_13,    0, 24, 0},
	{IPU_OSD_COLOR_14,		IPU_F_3_OSD_COLOR_14,    0, 24, 0},
	{IPU_CFG,		IPU_F_FRAME_ID_SET,    9, 16, 0},
	{IPU_CFG,		IPU_F_FRAME_ID_EN,     3,  6, 0},
	{IPU_CFG,		IPU_F_SRC_SEL,         0,  2, 0},
	{IPU_RD_DDR_ADDR_Y,		IPU_F_RD_DDR_ADDR_Y,     0, 32, 0},
	{IPU_RD_DDR_ADDR_UV,	IPU_F_RD_DDR_ADDR_UY,    0, 32, 0},
	{IPU_US_DDR_Y,			IPU_F_US_DDR_Y,          0, 32, 0},
	{IPU_US_DDR_UV,			IPU_F_US_DDR_UY,         0, 32, 0},
	{IPU_DS_0_DDR_Y,		IPU_F_DS_0_DDR_Y,        0, 32, 0},
	{IPU_DS_0_DDR_UV,		IPU_F_DS_0_DDR_UV,       0, 32, 0},
	{IPU_DS_1_DDR_Y,		IPU_F_DS_1_DDR_Y,        0, 32, 0},
	{IPU_DS_1_DDR_UV,		IPU_F_DS_1_DDR_UV,       0, 32, 0},
	{IPU_DS_2_DDR_Y,		IPU_F_DS_2_DDR_Y,        0, 32, 0},
	{IPU_DS_2_DDR_UV,		IPU_F_DS_2_DDR_UV,       0, 32, 0},
	{IPU_DS_3_DDR_Y,		IPU_F_DS_3_DDR_Y,        0, 32, 0},
	{IPU_DS_3_DDR_UV,		IPU_F_DS_3_DDR_UV,       0, 32, 0},
	{IPU_DS_4_DDR_Y,		IPU_F_DS_4_DDR_Y,        0, 32, 0},
	{IPU_DS_4_DDR_UV,		IPU_F_DS_4_DDR_UV,       0, 32, 0},
	{IPU_OSD_0_STA_0_BIN01,	IPU_F_OSD_STA_BIN_1_NUM,  16, 16, 0},
	{IPU_OSD_0_STA_0_BIN01,	IPU_F_OSD_STA_BIN_0_NUM,   0, 16, 0},
	{IPU_OSD_0_STA_0_BIN23,	IPU_F_OSD_STA_BIN_3_NUM,  16, 16, 0},
	{IPU_OSD_0_STA_0_BIN23,	IPU_F_OSD_STA_BIN_2_NUM,   0, 16, 0},
	{IPU_DDR_START,		IPU_F_DDR_START,		0, 1 , 0},
	{IPU_TEST_Y_SET, 	IPU_F_TEST_Y_SET,		0, 32, 0},
	{IPU_TEST_U_SET,	IPU_F_TEST_U_SET,       0, 32, 0},
	{IPU_TEST_V_SET,	IPU_F_TEST_V_SET,       0, 32, 0},
	{IPU_PRE_INT_SET,	IPU_F_PRE_INT_1_SET,   13, 13, 0},
	{IPU_PRE_INT_SET,	IPU_F_PRE_INT_0_SET,    0, 12, 0},
};

#endif
